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參數資料
| 型號： | IS61LV6464 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 64 Synchronous Pipelined SRAM(64K x 64 同步流水線靜態RAM) |
| 中文描述： | 64K的同步流水線× 64的SRAM（64K的× 64同步流水線靜態內存） |
| 文件頁數： | 1/17頁 |
| 文件大小： | 223K |
| 代理商： | IS61LV6464 |
ISSI
IS61LV6464
IS61LV6464
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
Integrated Silicon Solution, Inc.
PRELIMINARY
SR023-0D
06/01/98
1
This document contains preliminary data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We
assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc.
FEATURES
Fast access time:
– -100 MHz; 6 ns-83 MHz;
7 ns-75 MHz; 8 ns-66 MHz
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Pentium or linear burst sequence control
using MODE input
Five chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
Power-down control by ZZ input
JEDEC 128-Pin TQFP 14mm x 20mm
package
Single +3.3V power supply
2.5V V
CCQ
(I/O supply)
Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
Q
or V
CCQ
to alter their power-up state
ISSI
DESCRIPTION
The
ISSI
IS61LV6464 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-
performance, secondary cache for the Pentium, 680X0,
and PowerPC microprocessors. It is organized as 65,536
words by 64 bits, fabricated with
ISSI
's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls I/O1-I/O8,
BW2
controls I/O9-I/O16,
BW3
con-
trols I/O17-I/O24,
BW4
controls I/O25-I/O32,
BW5
controls
I/O33-I/O40,
BW6
controls I/O41-I/O48,
BW7
controls I/O49-
I/O56,
BW8
controls I/O57-I/O64, conditioned by
BWE
being
LOW. A LOW on
GW
input would cause all bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated inter-
nally by the IS61LV6464 and controlled by the
ADV
(burst
address advance) input pin.
Asynchronous signals include output enable (
OE
), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates
after the wake-up period. A LOW input, i.e., GND
Q
, on MODE
pin selects LINEAR Burst. A V
CCQ
(or no connect) on MODE
pin selects INTERLEAVED Burst.
PRELIMINARY
JUNE 1998
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IS61LV6464-100PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 Fast Synchronous SRAM |
| IS61LV6464-100TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64K x 64 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6464-6PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64K x 64 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6464-6PQI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 Fast Synchronous SRAM |
| IS61LV6464-6TQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
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