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參數資料
| 型號： | IS61SF12832-8.5B |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| 中文描述： | 128K X 32 CACHE SRAM, 8.5 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 112K |
| 代理商： | IS61SF12832-8.5B |
IS61SF12832
IS61SF12836
128K x 32, 128K x 36 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
FEATURES
Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns,
and 12 ns
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data
inputs and control signals
Pentium or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin TQFP and
119-pin PBGA package
Single +3.3V +10%, –5% power supply
Power-down snooze mode
DESCRIPTION
The
ISSI
IS61SF12832 and IS61SF12836 are high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 131,072
words by 32 bits or 36 bits, fabricated with
ISSI
's advanced
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls DQc,
BW4
controls DQd, conditioned by
BWE
being LOW. A LOW
on
GW
input would cause all bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
and controlled by the
ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
APRIL 2001
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
7.5
7.5
8.5
117
8
8
10
100
8.5
8.5
11
90
10
10
15
66
12
12
15
66
Units
ns
ns
MHz
相關PDF資料 |
PDF描述 |
|---|---|
| IS61SF12832-8.5TQ | 128K x 32, 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61SF12832-8B | Octal D-Type Transparent Latches With 3-State Outputs 20-PDIP -40 to 85 |
| IS61SF12832-8TQ | Octal D-Type Transparent Latches With 3-State Outputs 20-SO -40 to 85 |
| IS61SF12832-8TQI | Octal D-Type Transparent Latches With 3-State Outputs 20-SO -40 to 85 |
| IS61SF12836-10B | x36 Fast Synchronous SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS61SF25618-8.5TQI | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 8.5ns 100-Pin TQFP |
| IS61SF25618-8.5TQI-TR | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 8.5ns 100-Pin TQFP T/R |
| IS61SF51218T-10TQ | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Single 3.3V 8M-Bit 512K x 16 10ns 100-Pin TQFP |
| IS61SP12836-133B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-133TQ-T | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Quad 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP T/R |
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