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參數資料
| 型號： | IS61SF6432-10TQ |
| 英文描述： | 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| 中文描述： | 64K的× 32 SYNCHRONOU仛流，通過靜態內存 |
| 文件頁數： | 12/16頁 |
| 文件大小： | 480K |
| 代理商： | IS61SF6432-10TQ |
IS61SF6432
12
Integrated Circuit Solution Inc.
SSR004-0B
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-9
-10
Min.
Symbol
Parameter
Min. Max.
Max.
Unit
t
KC
Cycle Time
13
—
15
—
ns
t
KH
Clock High Time
6
—
6
—
ns
t
KL
Clock Low Time
6
—
6
—
ns
t
KQ
Clock Access Time
—
9
—
10
ns
t
KQX
(2)
Clock High to Output Invalid
2
—
2
—
ns
t
KQLZ
(2,3)
Clock High to Output Low-Z
0
—
0
—
ns
t
KQHZ
(2,3)
Clock High to Output High-Z
2
6
2
6
ns
t
OEQX
(2)
Output Disable to Output Invalid
0
—
0
—
ns
t
OEHZ
(2,3)
Output Disable to Output High-Z
—
6
—
6
ns
t
AS
Address Setup Time
2.5
—
2.5
—
ns
t
SS
Address Status Setup Time
2.5
—
2.5
—
ns
t
WS
Write Setup Time
2.5
—
2.5
—
ns
t
CES
Chip Enable Setup Time
2.5
—
2.5
—
ns
t
AH
Address Hold Time
0.5
—
0.5
—
ns
t
SH
Address Status Hold Time
0.5
—
0.5
—
ns
t
WH
Write Hold Time
0.5
—
0.5
—
ns
t
CEH
Chip Enable Hold Time
0.5
—
0.5
—
ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
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