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參數資料
| 型號： | IS61SF6432 |
| 英文描述： | Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 64K的× 32 SYNCHRONOU仛流，通過靜態內存 |
| 文件頁數： | 10/16頁 |
| 文件大小： | 480K |
| 代理商： | IS61SF6432 |
IS61SF6432
10
Integrated Circuit Solution Inc.
SSR004-0B
WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-9
-10
Min.
Symbol
Parameter
Min. Max.
Max.
Unit
t
KC
Cycle Time
13
—
15
—
ns
t
KH
Clock High Time
6
—
6
—
ns
t
KL
Clock Low Time
6
—
6
—
ns
t
AS
Address Setup Time
2.5
—
2.5
—
ns
t
SS
Address Status Setup Time
2.5
—
2.5
—
ns
t
WS
Write Setup Time
2.5
—
2.5
—
ns
t
DS
Data In Setup Time
2.5
—
2.5
—
ns
t
CES
Chip Enable Setup Time
2.5
—
2.5
—
ns
t
AVS
Address Advance Setup Time
2.5
—
2.5
—
ns
t
AH
Address Hold Time
1
—
1
—
ns
t
SH
Address Status Hold Time
0.5
—
0.5
—
ns
t
DH
Data In Hold Time
0.5
—
0.5
—
ns
t
WH
Write Hold Time
0.5
—
0.5
—
ns
t
CEH
Chip Enable Hold Time
0.5
—
0.5
—
ns
t
AVH
Address Advance Hold Time
0.5
—
0.5
—
ns
t
CFG
Configuration Setup
(1)
52
—
60
—
ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
相關PDF資料 |
PDF描述 |
|---|---|
| IS61SF6432-10PQ | Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85 |
| IS61SF6432-10PQI | 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61SF6432-10TQ | 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61SF6432-10TQI | Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85 |
| IS61SF6432-9PQ | Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS61SP12836-133B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-133TQ-T | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Quad 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP T/R |
| IS61SP12836-166B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-200B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP6464-100PQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
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