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參數資料
| 型號： | IS61SP12832-133TQ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM |
| 中文描述： | 128K的× 32 SYNCHRONOU擰流水線靜態RAM |
| 文件頁數： | 1/14頁 |
| 文件大小： | 490K |
| 代理商： | IS61SP12832-133TQ |
Integrated Circuit Solution Inc.
1
SSR011-0B
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Pentium or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin LQFP and
119-pin PBGA package
Single +3.3V, +10%, –5% power supply
Power-down snooze mode
DESCRIPTION
The
ICSI
IS61SP12832 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the Pentium, 680X0, and
PowerPC microprocessors. It is organized as 131,072
words by 32 bits, fabricated with
ICSI
's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls DQc,
BW4
controls DQd, conditioned by
BWE
being LOW. A LOW
on
GW
input would cause all bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP12832 and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
IS61SP12832
128K x 32 SYNCHRONOUS
PIPELINED STATIC RAM
FAST ACCESS TIME
Symbol
Parameter
-166
-150
-133
-117
-5
Units
t
KQ
Clock Access Time
3.5
3.8
4
4
5
ns
t
KC
Cycle Time
6
6.7
7.5
8.5
10
ns
Frenquency
166
150
133
117
100
MHz
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PDF描述 |
|---|---|
| IS61SP12832-150B | 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM |
| IS61SP12832-150TQ | 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM |
| IS61SP12832-166B | 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM |
| IS61SP12832-166TQ | 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IS61SP12836-133B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-133TQ-T | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Quad 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP T/R |
| IS61SP12836-166B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-200B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP6464-100PQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
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