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參數資料
| 型號： | IS61SP12836-166B |
| 英文描述： | x36 Fast Synchronous SRAM |
| 中文描述： | x36快速同步SRAM |
| 文件頁數： | 1/16頁 |
| 文件大小： | 108K |
| 代理商： | IS61SP12836-166B |
IS61SF25616
IS61SF25618
256K x 16, 256K x 18 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
FEATURES
Fast access times: 8 ns, 8.5 ns, 10 ns, and 12 ns
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data inputs
and control signals
Pentium
TM
or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin TQFP and
119-pin PBGA package
Single +3.3V +10%, –5% power supply
Power-down snooze mode
APRIL 2001
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
8
8
10
100
8.5
8.5
11
90
10
10
15
66
12
12
15
66
Units
ns
ns
MHz
DESCRIPTION
The
ISSI
IS61SF25616 and IS61SF25618 is a high-speed,
low-power synchronous static RAM designed to provide
a burstable, high-performance memory for high speed
networking and communication applications. It is organized
as 262,144 words by 16 bits and 18 bits, fabricated with
ISSI
's advanced CMOS technology. The device integrates
a 2-bit burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQ1-8,
BW2
controls DQ9-16, conditioned
by
BWE
being LOW. A LOW on
GW
input would cause all
bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61SF25616 and controlled by the
ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
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