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參數(shù)資料
| 型號(hào)： | IS62C1024-55T |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | TSOP1-32 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 423K |
| 代理商： | IS62C1024-55T |
6
Integrated Circuit Solution Inc.
SR016-0B
IS62C1024
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range, Standard and Low
Power)
-35
-45
-55
-70
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
35
—
45
—
55
—
70
—
ns
t
SCE
1
CE1
to Write End
25
—
35
—
50
—
60
—
ns
t
SCE
2
CE2 to Write End
25
—
35
—
50
—
60
—
ns
t
AW
Address Setup Time to Write End
25
—
35
—
45
—
60
—
ns
t
HA
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
t
SA
Address Setup Time
0
—
0
—
0
—
0
—
ns
t
PWE
(4)
WE
Pulse Width
25
—
35
—
40
—
50
—
ns
t
SD
Data Setup to Write End
20
—
25
—
25
—
30
—
ns
t
HD
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
t
HZWE
(2)
WE
LOW to High-Z Output
—
10
—
15
—
20
—
25
ns
t
LZWE
(2)
WE
HIGH to Low-Z Output
3
—
5
—
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with
OE
HIGH.
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WE
Controlled)
(1,2)
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| IS62C1024-70Q | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-70T | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-35T | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS62C1024-55TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-55W | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-55WI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-70Q | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 70ns 32-Pin SOP |
| IS62C1024-70QI | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 70ns 32-Pin SOP |
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