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參數(shù)資料
| 型號： | IS62C1024-55TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | TSOP1-32 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 423K |
| 代理商： | IS62C1024-55TI |
Integrated Circuit Solution Inc.
7
SR016-0B
IS62C1024
WRITE CYCLE NO. 2 (
CE1
, CE2 Controlled)
(1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS62C1024-70Q | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-70T | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-35T | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-35TI | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-45Q | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS62C1024-55W | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-55WI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS62C1024-70Q | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 70ns 32-Pin SOP |
| IS62C1024-70QI | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 70ns 32-Pin SOP |
| IS62C1024-70T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
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