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參數(shù)資料
型號(hào): IS62LV25616LL-70BI
英文描述: x16 SRAM
中文描述: x16的SRAM
文件頁(yè)數(shù): 1/10頁(yè)
文件大?。?/td> 91K
代理商: IS62LV25616LL-70BI
IS62LV25616LL
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
05/04/01
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
256K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
High-speed access time: 70 and 85 ns
CMOS low power operation
– 135 mW (typical) operating
– 16.5 W (typical) CMOS standby
TTL compatible interface levels
Single 2.7V (min) to 3.15V (max) VCC power supply
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (8mm x 10mm and 7.2mm x 8.7mm)
DESCRIPTION
The
ISSI IS62LV25616LL is high-speed, 4,194,304 bit
static RAM organized as 262,144 words by 16 bits. It is
fabricated using
ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When
CEisHIGH(deselected)orwhenCEislowandbothLBand
UB are HIGH, the device assumes a standby mode at which the
power dissipation can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs,
CEand OE.TheactiveLOWWriteEnable
(
WE)controlsbothwritingandreadingofthememory.Adatabyte
allows Upper Byte (
UB) and Lower Byte (LB) access.
The IS62LV25616LL is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA (8mm x 10mm
and 7.2mm x 8.7mm).
FUNCTIONAL BLOCK DIAGRAM
MAY 2001
A0-A17
CE
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
相關(guān)PDF資料
PDF描述
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