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參數資料
| 型號： | IS65LV256AL-45ULA3 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 LOW VOLTAGE CMOS STATIC RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 45 ns, PDSO28 |
| 封裝： | 0.330 MM, LEAD FREE, PLASTIC, SOP-28 |
| 文件頁數： | 1/14頁 |
| 文件大?。?/td> | 113K |
| 代理商： | IS65LV256AL-45ULA3 |
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
03/17/06
1
ISSI
Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
IS65LV256AL
IS62LV256AL
FEATURES
High-speed access time: 20, 45 ns
Automatic power-down when chip is deselected
CMOS low power operation
— 17 μW (typical) CMOS standby
— 50 mW (typical) operating
TTL compatible interface levels
Single 3.3V power supply
Fully static operation: no clock or refresh
required
Three-state outputs
Industrial and Automotive temperatures avail-
able
Lead-free available
DESCRIPTION
The
ISSI
IS62/65LV256AL is a very high-speed, low
power, 32,768-word by 8-bit static RAM. It is fabricated
using
ISSI
's high-performance CMOS technology. This
highly reliable process coupled with innovative circuit
design techniques, yields access times as fast as 15 ns
maximum.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
150 μW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (
CE
). The active LOW Write Enable
(
WE
) controls both writing and reading of the memory.
The IS62/65LV256AL is available in the JEDEC standard
28-pin SOJ, 28-pin SOP, and the 28-pin 450-mil TSOP
package.
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
32K x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
MARCH 2006
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