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參數資料
| 型號： | IS65WV25616ALL-70TA3 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 70 ns, PDSO44 |
| 封裝： | PLASTIC, TSOP2-44 |
| 文件頁數： | 1/13頁 |
| 文件大小： | 109K |
| 代理商： | IS65WV25616ALL-70TA3 |
IS65WV25616ALL
IS65WV25616BLL
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00B
06/20/06
1
Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
256K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC SRAM
FEATURES
High-speed access time: 55ns, 70ns
CMOS low power operation
36 mW (typical) operating
9 μW (typical) CMOS standby
TTL compatible interface levels
Single power supply
1.65V--2.2V V
DD
(65WV25616ALL)
2.5V--3.6V V
DD
(65WV25616BLL)
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
TEMPERATURE OFFERINGS:
Option A1: -40°C to +85°C
Option A2: -40°C to +105°C
Option A3: -40°C to +125°C
Lead-free available
DESCRIPTION
The
ISSI
IS65WV25616ALL/IS65WV25616BLL are high-
speed, low power, 4M bit SRAMs organized as 256K words
by 16 bits. It is fabricated using
ISSI
's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When
CS1
is HIGH (deselected) or when
CS1
is LOW, and
both
LB
and
UB
are HIGH, the device assumes a standby
mode at which the power dissipation can be reduced down
with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE)
controls both writing and reading of the memory. A
data byte allows Upper Byte
(UB)
and Lower Byte (
LB)
access.
The IS65WV25616BALL/65WV25616BLL are packaged in
the JEDEC standard 44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
PRELIMINARY INFORMATION
JUNE 2006
A0-A17
CS1
OE
WE
UB
LB
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
25616LL_BLK.eps
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| IS65WV25616BLL | 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS65WV25616BLL-55TA1 | 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS65WV25616BLL-55TLA1 | 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS65WV25616BLL-70TA2 | 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS65WV25616BLL-70TA3 | 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS65WV25616BLL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS65WV25616BLL-55TA1 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS65WV25616BLL-55TLA1 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS65WV25616BLL-70TA2 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
| IS65WV25616BLL-70TA3 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM |
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