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參數資料
| 型號： | ISL6225 |
| 廠商： | Intersil Corporation |
| 英文描述： | Dual Mobile-Friendly PWM Controller with DDR Memory Option(帶DDR存儲器選項的雙移動型PWM控制器) |
| 中文描述： | 雙移動友好PWM控制器與DDR內存選項（帶的DDR存儲器選項的雙移動型脈寬調制控制器） |
| 文件頁數： | 1/19頁 |
| 文件大小： | 522K |
| 代理商： | ISL6225 |
1
ISL6225
Dual Mobile-Friendly PWM Controller with
DDR Memory Option
The ISL6225 dual PWM controller delivers high efficiency and
tight regulation from two voltage regulating synchronous buck
DC/DC converters. The ISL6225 PWM power supply controller
was designed especially for DDR DRAM, SDRAM, and graphic
chipset applications in high performance desknote PCs,
notebook PCs, sub-notebook PCs, and PDAs.
Automatic mode selection of constant-frequency synchronous
rectification at heavy load, and hysteretic diode-emulation at
light load, assure high efficiency over a wide range of
conditions. The hysteretic mode of operation can be disabled
separately on each PWM converter if constant-frequency
continuous-conduction operation is desired for all load levels.
Efficiency is further enhanced by using the lower MOSFET
r
DS(ON)
as the current sense element.
Voltage-feed-forward ramp modulation, average current mode
control, and internal feedback compensation provide fast
response to input voltage and output load transients. Input
current ripple is minimized by channel to channel PWM
phase shift of 0°, 90°, or 180° determined by input voltage
and status of the DDR pin.
The ISL6225 can control two independent output voltages
adjustable from 0.9V to 5.5V or, by activating the DDR pin,
transform into a complete DDR memory power supply
solution. In DDR mode, CH2 output voltage VTT tracks CH1
output voltage VDDQ. CH2 output can both source and sink
current, an essential power supply feature for DDR memory
systems. The reference voltage VREF required by DDR
memory is generated as well.
In dual power supply applications the ISL6225 monitors the
output voltage of both CH1 and CH2. An independent
PGOOD (power good) signal is asserted for each channel
after the soft-start sequence has completed, and the output
voltage is within ±10% of the set point. In DDR mode CH1
generates the only PGOOD signal.
Built-in overvoltage protection prevents the output from
going above 115% of the set point by holding the lower
MOSFET on and the upper MOSFET off. When the output
voltage decays below the overvoltage threshold, normal
operation automatically resumes. Once the soft-start
sequence has completed, under-voltage protection may
latch the ISL6225 off if either output drops below 75% of its
set point value.
Adjustable overcurrent protection (OCP) monitors the
voltage drop across the r
DS(ON)
of the lower MOSFET. If
more precise current-sensing is required, an external current
sense resistor may be used.
Features
Provides regulated output voltage in the range of 0.9V-5.5V
- High efficiency over wide load range
- Synchronous buck converter with hysteretic operation at
light load
- Inhibit Hysteretic mode on one, or both channels
Complete DDR memory power solution
- VTT tracks VDDQ/2
- VDDQ/2 buffered reference output
No current-sense resistor required
- Uses MOSFET r
DS(ON)
- Optional current-sense resistor for precision overcurrent
Under-voltage lock-out on V
CC
pin
Dual input voltage mode operation
- Operates directly from battery 5V to 24V input
- Operates from 3.3V or 5V system rail
- VCC from 5V only
Excellent dynamic response
- Combined voltage feed-forward and average current
mode control
Power-good signal for each channel
300kHz switching frequency
- 180° channel to channel phase operation for reduced input
ripple when not in DDR mode
- 0° channel to channel phase operation in DDR mode for
reduced channel interference
- 90° channel to channel phase operation for reduced input
ripple in DDR mode when VIN is at GND.
Pb-Free Available (RoHS Compliant)
Applications
Mobile PCs
PDAs
Hand-held portable instruments
Ordering Information
PART NUMBER
TEMP. (°C)
PACKAGE
PKG.
DWG. #
ISL6225CA
-10 to 85
28 Ld SSOP
M28.15
ISL6225CAZ (Note 1)
-10 to 85
28 Ld SSOP (Pb-free) M28.15
ISL6225CAZA (Note 1)
-10 to 85
28 Ld SSOP (Pb-free) M28.15
NOTES:
1. Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-T” for Tape and Reel.
ISL6227 OR ISL6539
December 28, 2004
FN9049.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002-2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT:
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISL6225BCA-T | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| ISL6225CA | 功能描述:IC CTRLR DDR DRAM, SDRAM 28QSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩壓器 - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數:10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR) |
| ISL6225CA-T | 功能描述:IC CTRLR DDR DRAM, SDRAM 28QSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩壓器 - 專用型 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,000 系列:- 應用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數:10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應商設備封裝:42-WLP 包裝:帶卷 (TR) |
| ISL6225CAZ | 功能描述:電流型 PWM 控制器 DL SWITCHER W/DRR OPTION 30V CS80 FSC RoHS:否 制造商:Texas Instruments 開關頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| ISL6225CAZA | 功能描述:電流型 PWM 控制器 W/ANNEAL DL SWITCHER W/DRR OPTION 30V RoHS:否 制造商:Texas Instruments 開關頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數量:1 最大工作溫度:+ 105 C 安裝風格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
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