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| 型號(hào)： | ISLA214S50IR1Z |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 1/41頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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14-Bit, 500/350 MSPS JESD204B High Speed Serial
Output ADC
ISLA214S50
The ISLA214S50 is a series of low-power, high-performance,
14-bit, analog-to-digital converters. Designed with
FemtoCharge technology on a standard CMOS process, the
series supports sampling rates of up to 500MSPS. The
ISLA214S50 is part of a pin-compatible family of 12-, 14-, and
16-bit A/Ds with maximum sample rates ranging from
125MSPS to 500MSPS. The family minimizes power
consumption while providing state-of-the-art dynamic
performance.
The device utilizes two time-interleaved 250MSPS unit ADCs to
achieve the ultimate sample rate of 500MSPS. A single
500MHz conversion clock is presented to the converter, and all
interleave clocking is managed internally. The proprietary
Intersil Interleave Engine (I2E) performs automatic correction
of offset, gain, and sample time mismatches between the unit
ADCs to optimize performance.
The ISLA214S50 offers a highly configurable, JESD204B-
compliant, high speed serial output link. The link offers data
rates up to 4.375 Gbps per lane and multiple packing modes.
The link can be configured to use two or three lanes to
transmit the conversion data, allowing for flexibility in the
receiver design. The JESD204 transmitter also provides
deterministic latency and multi-chip time alignment support to
satisfy complex synchronization requirements.
A serial peripheral interface (SPI) port allows for extensive
configurability of the ADC and its JESD204B transmitter
including access to its built-in link and transport-layer test
patterns as well as the programmable clock divider, enabling
2x harmonic clocking.
The ISLA214S50 is available in a space-saving 7mmx7mm 48
Ld QFN package. The package features a thermal pad for
improved thermal performance and is specified over the full
industrial temperature range (-40°C to +85°C)
Features
JESD204A/B High Speed Data Interface
-JESD204A Compliant
- JESD204B Device Subclass 0 Compliant
- JESD204B Device Subclass 2 Compatible
- Up to 3 JESD204 Output Lanes Running up to 4.375Gbps
- Highly Configurable JESD204 Transmitter
Multiple Chip Time Alignment and Deterministic Latency
Support (JESD204B Device Subclass 2)
SPI Programmable Debugging Features and Test Patterns
48-pin QFN 7mmx7mm Package
Key Specifications
SNR @ 500/350MSPS
73.1/74.1 dBFS fIN = 30MHz
71.0/71.6 dBFS fIN = 363MHz
SFDR @ 500/350MSPS
87/87 dBc fIN = 30MHz
78/81 dBc fIN = 363MHz
Total Power Consumption: 1060mW @ 500MSPS
Applications
Radar and Satellite Antenna Array Processing
Broadband Communications and Microwave Receivers
High-Performance Data Acquisition
Communications Test Equipment
High-Speed Medical Imaging
+
FIGURE 1. SERDES DATA EYE AT 4.375Gbps
Pin-Compatible Family
MODEL
RESOLUTION
SPEED
(MSPS)
PRODUCT
AVAILABILITY
ISLA214S50
14
500
Now
ISLA214S35
14
350
Soon
April 25, 2013
FN7973.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Copyright Intersil Americas LLC 2011, 2013. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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