
ISO107
6
NOTES: (1) Enable = pin open
or TTL high. (2) Ground sync if
not used. (3)
π
filter reduces
ripple current: L
I
= 10
μ
H, <10
.
THEORY OF OPERATION
The block diagram on the front page shows the isolation
amplifier’s synchronized signal and power configuration,
which eliminates beat frequency interference. A proprietary
800kHz oscillator chip, power MOSFET transformer driv-
ers, patented square core wirebonded transformer, and single
chip diode bridge provide power to the input side of the
isolation amplifier as well as external loads. The signal
channel capacitively couples a duty-cycle encoded signal
across the ceramic high-voltage barrier built into the pack-
age. A proprietary transmitter-receiver pair of integrated
circuits, laser trimmed at wafer level, and coupled through a
pair of matched “fringe” capacitors, result in a simple,
reliable design.
SIGNAL AND POWER CONNECTIONS
Figure 1 shows the proper power supply and signal connec-
tions. All power supply pins should be bypassed as shown
with the
π
filter for +V
an option recommended if more
than
±
15mA are drawn from the isolated supply. The sepa-
rate input and output common pins and output sense are low
current inputs tied to the signal source ground, output
ground, and output load, respectively, to minimize errors
due to IR drop in long conductors. Otherwise, connect Com
1 to Gnd 1, Com 2 to Gnd 2, and Sense to V
at the ISO107
socket. The enable pin may be left open if the ISO107 is
continuously operated. If not, a TTL low level will disable
the internal DC/DC converter. The Sync input must be
grounded for unsynchronized operation while a 1.2MHz to
2MHz TTL clock signal provides synchronization of mul-
tiple units.
OPTIONAL GAIN AND OFFSET ADJUSTMENTS
Rated gain accuracy and offset performance can be achieved
with no external adjustments, but the circuit of Figure 2a
may be used to provide a gain trim of
±
0.5% for the values
shown; greater range may be provided by increasing the size
of R1 and R1. Every 2k
increase in R1 will give an
additional 1% adjustment range, with R2
≥
R1. If safety or
convenience dictates location of the adjustment potentiome-
ter on the other side of the barrier from the position shown
in Figure 2a, the position of R1 and R2 may be reserved.
Gains greater than 1 may be obtained by using the circuit of
Figure 2b. Note that the effect of input offset errors will be
multiplied at the output in proportion to the increase in gain.
Also, the small-signal bandwidth will be decreased in in-
FIGURE 1. Signal and Power Connections.
FIGURE 2b. Gain Setting.
V
IN
30
29
15
14
13
V
OUT
Sense
R
1
R
2
Gain = 1 + R
1
R
1
( )
FIGURE 2a. Gain Adjust.
1k
V
IN
R
1
30
29
2k
R
2
15
14
13
V
OUT
*Optional Filtering:
L
O
= 10
μ
H, <10
C
O
= 0.1 – 10pF
NC
Gnd 1
Sync
(2)
–V
CC2
31
30
29
20
19
18
17
Enable
(1)
+V
CC2
1μF
L
I
(3)
1μF
10μF Tantalum
+
16
15
14
13
Sense
V
OUT
Com 2
Com Return
–V
CC1
+V
CC1
V
IN
Com 1
NC
NC
+V
CC1
–V
CC1
ISO107
*
*
C
O
C
O
*
*
L
O
L
O
V
IN
Com
Isolation Barrier
4
2
1μF
max*
+V
CC2
–V
CC2
Com 2
V
OUT
Sense Gnd 2
1μF
max*
C
1
C
2