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參數資料
| 型號： | ISP1181BBS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC48 |
| 封裝： | 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48 |
| 文件頁數： | 28/70頁 |
| 文件大小： | 341K |
| 代理商： | ISP1181BBS |
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Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
28 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
12.1.4
Write/Read Hardware Configuration
This command is used to access the Hardware Configuration Register, which
consists of 2 bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in
Table 20
. A bus reset will not change any
of the programmed bit values.
The Hardware Configuration Register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB —
write/read Hardware Configuration Register
Transaction —
write/read 2 bytes
Table 20:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Hardware Configuration Register: bit allocation
15
14
reserved
EXTPUL
0
0
R/W
R/W
7
6
DAKOLY
DRQPOL
0
1
R/W
R/W
13
12
11
10
9
8
NOLAZY
1
R/W
5
DAKPOL
0
R/W
CLKRUN
0
R/W
4
EOTPOL
0
R/W
CLKDIV[3:0]
0
0
1
1
R/W
3
R/W
2
R/W
1
INTLVL
0
R/W
R/W
0
INTPOL
0
R/W
WKUPCS
0
R/W
PWROFF
0
R/W
Table 21:
Bit
15
14
Hardware Configuration Register: bit description
Symbol
Description
-
reserved
EXTPUL
A logic 1 indicates that an external 1.5 k
pull-up resistor is
used on pin D
+
and that SoftConnect is not used. Bus reset
value: unchanged.
NOLAZY
A logic 1 disables output on pin CLKOUT of the LazyClock
frequency (100 kHz
±
50 %) during ‘suspend’ state. A logic 0
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
in the Mode Register. Bus reset value: unchanged.
CLKRUN
A logic 1 indicates that the internal clocks are always running,
even during ‘suspend’ state. A logic 0 switches off the internal
oscillator and PLL, when they are not needed. During ‘suspend’
state this bit must be made logic 0 to meet the suspend current
requirements. The clock is stopped after a delay of
approximately 2 ms, following the setting of bit GOSUSP in the
Mode Register. Bus reset value: unchanged.
CLKDIV[3:0]
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by
3 MHz to 48 MHz (N = 0 to 15). with a reset value of 12 MHz
(N = 3). The hardware design guarantees no glitches during
frequency change. Bus reset value: unchanged.
DAKOLY
A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237
compatible DMA mode. Bus reset value: unchanged.
13
12
11 to 8
. The clock frequency range is
7
48
N
1
+
(
)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISP1181BBS,518 | 功能描述:USB 接口集成電路 USB 1.1 DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181BBS,551 | 功能描述:USB 接口集成電路 USB 1.1 DEVICE CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181BBS,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1181BBS518 | 制造商:ST-Ericsson 功能描述:CONTROLLER USB PERIPHERAL 48HVQFN |
| ISP1181BBSGE | 功能描述:IC USB CNTRLR FULL-SPD 48-HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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