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參數資料
| 型號： | ISPGAL22V10B-10LJ |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable E2CMOS PLD |
| 中文描述： | EE PLD, 10 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 247K |
| 代理商： | ISPGAL22V10B-10LJ |
Specifications
ispGAL22V10
ispGAL22V10
In-System Programmable E
2
CMOS PLD
Generic Array Logic
1
IN-SYSTEM PROGRAMMABLE (5-V ONLY)
— 4-Wire Serial Programming Interface
— Minimum 10,000 Program/Erase Cycles
— Built-in Pull-Down on SDI Pin Eliminates Discrete
Resistor on Board (ispGAL22V10C Only)
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5 ns Maximum from Clock Input to Data Output
— UltraMOS
Advanced CMOS Technology
ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
E
2
CELL TECHNOLOGY
— In-System Programmable Logic
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Software-Driven Hardware Configuration
ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
The ispGAL22V10, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E
2
) floating gate technology to provide the industry's
first in-system programmable 22V10 device. E
2
technology of-
fers high speed (<100ms) erase times, providing the ability to re-
program or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The ispGAL22V10 is fully function/fuse map/parametric
compatible with standard bipolar and CMOS 22V10 devices. The
standard PLCC package provides the same functional pinout as
the standard 22V10 PLCC package with No-Connect pins being
used for the ISP interface signals.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 10,000 erase/write
cycles and data retention in excess of 20 years are specified.
FUNCTIONAL BLOCK DIAGRAM
FEATURES
PIN CONFIGURATION
P
A
(
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
SDI
MODE
SCLK
I/CLK
I
I
I
I
I
I
I
I
I
I
RESET
PRESET
8
10
12
14
16
16
14
12
10
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
PROLOGIC
I
Copyright 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
PLCC
SDO
I/O/Q
I/O/Q
I/O/Q
2
28
I
I
MODE
I
I
I
5
11
14
16
19
25
4
7
9
12
18
21
23
26
I
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
I
V
S
I
I
I
S
G
I
I
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
SDI
SCLK
I/CLK
I
I
I
I
I
MODE
I
I
I
I
I
GND
1
7
14
28
22
15
ispGAL
22V10
Top View
SSOP
ispGAL22V10
Top View
isp22v10_02
相關PDF資料 |
PDF描述 |
|---|---|
| ISPGAL22V10B-15LJ | 16-Wide LVDS Receiver w/Integrated Termination |
| ISPGAL22V10 | In-System Programmable E2CMOS PLD |
| ISPGAL22V10B-7LJ | In-System Programmable E2CMOS PLD |
| ISPGAL22V10C-15LJ | In-System Programmable E2CMOS PLD |
| ISPGAL22V10C-15LJI | In-System Programmable E2CMOS PLD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISPGAL22V10B-15LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable E2CMOS PLD |
| ISPGAL22V10B-7LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable E2CMOS PLD |
| ISPGAL22V10C-10LJ | 功能描述:SPLD - 簡單可編程邏輯器件 5V 22 I/O RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPGAL22V10C-10LJI | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPGAL22V10C-10LJN | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE LO VOLT E2CMOS PLD RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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