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參數(shù)資料
| 型號(hào)： | ISPLSI 2064A-100LJN84 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 64I/O 10NS 84PLCC |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | ispLSI® 2000A |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 64 |
| 門數(shù)： | 2000 |
| 輸入/輸出數(shù)： | 64 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.31x29.31） |
| 包裝： | 管件 |
| 其它名稱： | ISPLSI2064A-100LJN84 |
ispLSI
2064/A
In-System Programmable High Density PLD
2064_10
1
USE
ispLSI
2064E
FOR
NEW
DESIGNS
Lead-
Free
Package
Options
Available!
Features
ENHANCEMENTS
— ispLSI 2064A is Fully Form and Function Compatible
to the ispLSI 2064, with Identical Timing
Specifcations and Packaging
— ispLSI 2064A is Built on an Advanced 0.35 Micron
E2CMOS Technology
HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
HIGH PERFORMANCE E2CMOS TECHNOLOGY
—
fmax = 125 MHz Maximum Operating Frequency
—
tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Fu
Description
The ispLSI 2064 and 2064A are High Density Program-
mable Logic Devices. The devices contain 64 Registers,
64 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The 2064 and 2064A feature 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 2064 and 2064A offer non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…B7
(Figure 1). There are a total of 16 GLBs in the ispLSI 2064
and 2064A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
Input
Bus
Output
Routing
Pool
(ORP)
B3
B2
B1
B0
Input
Bus
Output
Routing
Pool
(ORP)
A2
GLB
Logic
Array
DQ
A4
A5
A6
A7
Input Bus
Output Routing Pool (ORP)
B7
B6
B5
B4
Input Bus
Output Routing Pool (ORP)
0139Bisp/2064
Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ispLSI2064A-100LJN84 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ispLSI2064A-100LT100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064A100LT100I | 制造商:LATTICE 功能描述:New |
| ispLSI2064A-100LTN100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ispLSI2064A-125LJ84 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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