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參數資料
| 型號： | ISPLSI 2096E-135LT128 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數： | 1/11頁 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 96I/O 7.5NS 128TQFP |
| 標準包裝： | 90 |
| 系列： | ispLSI® 2000E |
| 可編程類型： | 系統內可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數目： | 24 |
| 宏單元數： | 96 |
| 門數： | 4000 |
| 輸入/輸出數： | 96 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI2096E-135LT128 |
ispLSI
2096E
In-System Programmable
SuperFAST High Density PLD
2096e_04
1
Features
SUPERFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional/JEDEC Upward Compatible with
ispLSI 2096 Devices
HIGH PERFORMANCE E2CMOS TECHNOLOGY
—
fmax = 180 MHz Maximum Operating Frequency
—
tpd = 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O Supports Mixed-
Voltage Systems
— PCI Compatible Outputs
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Functional Block Diagram
Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
Description
The ispLSI 2096E is a High Density Programmable Logic
Device. The device contains 96 Registers, 96 Universal
I/O pins, six Dedicated Input pins, three Dedicated Clock
Input pins, two dedicated Global OE input pins and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 2096E features 5V in-system programmability
and in-system diagnostic capabilities. The ispLSI 2096E
offers non-volatile reprogrammability of all logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
The basic unit of logic on the ispLSI 2096E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or
registered.Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro-
grammed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
Global Routing Pool
(GRP)
Output Routing Pool (ORP)
0919/2096E
C7
C4
C5
C6
A4
A7
A6
A5
GLB
Logic
Array
DQ
Output Routing Pool (ORP)
C3
C0
C1
C2
B0
B3
B2
B1
Output
Routing
Pool
(ORP)
Output
Routing
Pool
(ORP)
B7
B6
B4
B5
A0
A1
A3
A2
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISPLSI2096E-135LT128 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2096E-180LQ128 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2096E-180LT128 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2096V-60LQ128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI2096V-60LT128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
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