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參數資料
| 型號： | ISPLSI2064V-100LJ84I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V High Density Programmable Logic |
| 中文描述： | 3.3高密度可編程邏輯 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 179K |
| 代理商： | ISPLSI2064V-100LJ84I |
ispLSI
2064V
3.3V High Density Programmable Logic
2064v_10
1
USEispLS 2064VEFORNEWDESGNS
Features
HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
— The 64 I/O Pin Version is Fuse Map Compatible with
5V ispLSI 2064
HIGH-PERFORMANCE E
CMOS
TECHNOLOGY
—
f
max
= 100MHz Maximum Operating Frequency
—
t
pd
= 7.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERT – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER
— PC and UNIX Platforms
Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
I
B3
B2
B1
B0
I
A2
GLB
Logic
Array
D Q
D Q
D Q
D Q
A4
A5
A6
A7
B7
B6
B5
B4
Input Bus
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
0139A/2064V
Description
The ispLSI 2064V is a High Density Programmable Logic
Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064V features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP). The ispLSI 2064V offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064V device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
相關PDF資料 |
PDF描述 |
|---|---|
| ISPLSI2064V-100LT100 | 3.3V High Density Programmable Logic |
| ISPLSI2064V-100LT100I | 3.3V High Density Programmable Logic |
| ISPLSI2064V-100LT44 | 3.3V High Density Programmable Logic |
| ISPLSI2064V-100LT44I | 3.3V High Density Programmable Logic |
| ISPLSI2064VE-135LJ44 | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISPLSI2064V100LT100 | 制造商:LATT 功能描述: |
| ISPLSI2064V-100LT100 | 制造商:Lattice Semiconductor Corporation 功能描述:COMPLEX-EEPLD, 64-CELL, 12NS PROP DELAY, 100 Pin, Plastic, QFP |
| ISPLSI2064V-100LT100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2064V-100LT44 | 制造商:Lattice Semiconductor Corporation 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:EE PLD, 12 ns, PQFP44 |
| ISPLSI2064V-100LT44I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
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