- 您現(xiàn)在的位置：買賣IC網 > PDF目錄19778 > ISPLSI2192VE-100LB144 (Lattice Semiconductor Corporation)IC PLD ISP 96I/O 10NS 144FPBGA PDF資料下載
參數(shù)資料
| 型號： | ISPLSI2192VE-100LB144 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 96I/O 10NS 144FPBGA |
| 標準包裝： | 160 |
| 系列： | ispLSI® 2000VE |
| 可編程類型： | 系統(tǒng)內可編程 |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 48 |
| 宏單元數(shù)： | 192 |
| 門數(shù)： | 8000 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA |
| 供應商設備封裝： | 144-FPBGA（13x13） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI 2192VE-100LB144 ISPLSI 2192VE-100LB144-ND Q6436683 |
ispLSI
2192VE
3.3V In-System Programmable
SuperFAST High Density PLD
2192ve_10
1
Features
SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 8000 PLD Gates
— 96 I/O Pins, Nine or Twelve Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Pinout Compatible with ispLSI 2096V and 2096VE
3.3V LOW VOLTAGE ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
HIGH PERFORMANCE E2CMOS TECHNOLOGY
—
fmax = 225MHz Maximum Operating Frequency
—
tpd = 4.0ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-
OR Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
LEAD-FREE PACKAGE OPTIONS
Functional Block Diagram
Description
The ispLSI 2192VE is a High Density Programmable
Logic Device containing 192 Registers, nine or twelve
Dedicated Input pins, three Dedicated Clock Input pins,
two dedicated Global OE input pins and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements.
The ispLSI 2192VE
features in-system programmability through the Bound-
ary Scan Test Access Port (TAP) and is 100% IEEE
1149.1 Boundary Scan Testable. The ispLSI 2192VE
offers non-volatile reprogrammability of the logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
The basic unit of logic on the ispLSI 2192VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 2192VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
August 2004
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
Output
Routing
Pool
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
C0 C1 C2 C3 C4 C5 C6 C7
CLK0
CLK1
CLK2
D7
D6
D5
D4
D3
D2
D1
D0
Output
Routing
Pool
Logic
Array
DQ
Global Routing Pool (GRP)
GLB
0139/2192VE
Lead-
Free
Package
Options
Available!
相關PDF資料 |
PDF描述 |
|---|---|
| LTM4615EV#PBF | IC SWIT REG BUCK 4A ADJ 144LGA |
| MECT-110-01-M-D-RA1 | CONN RECEPT XFP 20POS SMD R/A |
| LLA319R71C224MA01L | CAP CER 0.22UF 16V 20% X7R 1206 |
| LC4128ZC-75T100E | IC PLD 128MC 64I/O 7.5NS 100TQFP |
| LC4128ZC-75TN100E | IC CPLD 128MACROCELLS 100TQFP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2192VE-100-LB144 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2192VE100LB144I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2192VE-100LT | 制造商:Lattice Semiconductor Corporation 功能描述:2192VE-100LT |
| ISPLSI2192VE100LT128 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2192VE-100LT128 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
發(fā)布緊急采購，3分鐘左右您將得到回復。