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參數資料
| 型號： | ISPLSI5512VE-100LF256 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 120K |
| 代理商： | ISPLSI5512VE-100LF256 |
ispLSI
1048
In-System Programmable High Density PLD
1
COMMERCAL&INDUSTRAL
DESGNS
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
1048_06
Functional Block Diagram
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool
Output Routing Pool
CLK
E7 E6 E5 E4 E3 E2 E1 E0
C0 C1 C2 C3 C4 C5 C6 C7
D7
D6
D5
D4
D3
D2
D1
D0
O
Logic
Array
D Q
D Q
D Q
D Q
Global Routing Pool (GRP)
GLB
Description
The ispLSI 1048 is a High-Density Programmable Logic
Device which contain 288 Registers, 96 Universal I/O
pins, ten Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1048 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1048 devices is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 (see figure 1). There are a total of 48 GLBs in the
ispLSI 1048 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
Features
HIGH-DENSITY PROGRAMMABLE LOGIC
— 8000 PLD Gates
— 96 I/O Pins, Ten Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Security Cell Prevents Unauthorized Copying
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
—
f
max
= 80 MHz Maximum Operating Frequency
—
f
max
= 50 MHz for Industrial Devices
—
t
pd
= 15 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E
2
CMOS Technology
— 100% Tested
IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERT – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER
— PC and UNIX Platforms
Copyright 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
相關PDF資料 |
PDF描述 |
|---|---|
| ISPLSI5512VE-100LF256I | Electrically-Erasable Complex PLD |
| ISPLSI5512VE-100LF388 | |
| ISPLSI5512VE-100LF388I | Electrically-Erasable Complex PLD |
| ISPLSI5512VE-125LB272 | |
| ISPLSI5512VE-125LB272I | Electrically-Erasable Complex PLD |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ISPLSI5512VE-100LF256-80I | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI5512VE-100LF256I | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VE-100LF388 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VE-100LF388I | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VE-125LB272 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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