
ispPAC 80
In-System Programmable Analog Circuit
pac80_03
1
TM
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-888-477-7537; FAX (503) 268-8037; http://www.latticesemi.com
March 2000
Functional Block Diagram
Features
IN-SYSTEM PROGRAMMABLE (ISP) ANALOG
— Instrument Amplifier Gain Stage
— Precision Active Filtering (50kHz to 500kHz)
— Continuous-Time Fifth Order Low Pass Topology
— Dual, A/B Configuration Memory
— Non-Volatile E
2
CMOS Cells
— IEEE 1149.1 JTAG Serial Port Programming
UNIQUE FLEXIBILITY AND PERFORMANCE
— Programmable Gain Range (0dB to 20dB)
— Implements Multiple Filter Types: Elliptical,
Chebyshev, Bessel, Butterworth, Linear Phase,
Gaussian and Legendre
— Low Distortion (THD < -74dB max @ 100kHz)
— Auto-Calibrated Input Offset Voltage
TRUE DIFFERENTIAL I/O
— High CMR (58dB) Instrument Amplifier Input
— 2.5V Common Mode Reference on Chip
— Rail-to-Rail Voltage Outputs
SINGLE SUPPLY 5V OPERATION
— Power Dissipation of 165mW
— 16-Pin Plastic SOIC, PDIP Packages
APPLICATIONS INCLUDE INTEGRATED
— Single +5V Supply Signal Conditioning
— Programmable Filters With Fully Differential I/O
— Analog Front Ends, 12-Bit Data Acq. Systems
— DSP System Front End Signal Conditioning
— High-Performance Reconstruction Filters
Typical Application Diagram
Description
The ispPAC80 is a member of the Lattice family of In-System
Programmable analog circuits, digitally configured via non-
volatile E
2
CMOS
technology.
Analog building blocks, called PACell(s), replace traditional
analog components such as opamps, eliminating the need for
external resistors and capacitors. With no requirement for
external configuration components, ispPAC80 expedites the
design process, simplifying prototype circuit implementation
and change, while providing high-performance integrated func-
tionality. With all components on chip, there is no longer a
concern of performance degradation due to component mis-
match or other external factors. The ispPAC80 provides reliable
and repeatable performance, every time.
Designers configure the ispPAC80 and verify its performance
using PAC-Designer, an easy to use, Microsoft Windows
compatible program. A filter configuration database is provided
whereby thousands of different configurations can be realized.
No special understanding of filter synthesis is required beyond
that of general specifications such as corner frequency and
stopband attenuation, etc. The software lists the possible
choices that meet the designer’s specifications which can then
be loaded directly into either of two device
(A/B) configurations from the lookup table. Device program-
ming is supported using PC parallel port I/O operations.
The ispPAC80 is configured through its IEEE Standard 1149.1
compliant serial port. The flexible In-System Programming
capability enables programming, verification and reconfig-
uration, if desired, directly on the printed circuit board.
Vin
VREFout
A/B & Gain
SPI Control
Reference
Ain-
Ain+
12-Bit Differential
Input ADC
DSP
ispPAC80
5V
5V
5V
OUT+
OUT
–
IN+
IN
–
VS
VREFOUT
TEST
TEST
E2CMOS Cfg A
Ref & Auto-Cal
ISP Control
E2CMOS Cfg B
IA
OA
5th Order LPF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TDI
TDO
TCK
TMS
GND
CAL
ENSPI
CS
ispPAC80