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參數(shù)資料
| 型號： | K4H560438D-TCA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Quad Wide Bandwidth High Output Drive Single Supply Op Amp 16-SOIC 0 to 70 |
| 中文描述： | 128MB DDR SDRAM的 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大小： | 291K |
| 代理商： | K4H560438D-TCA2 |
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256Mb
DDR SDRAM
Rev. 2.2 Mar. ’03
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Four banks operation
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
Data I/O transactions on both edges of data strobe
Edge aligned data output, center aligned data input
LDM,UDM/DM for write masking only
Auto & Self refresh
7.8us refresh interval(8K/64ms refresh)
Maximum burst refresh cycle : 8
60 Ball FBGA package
Key Features
Operating Frequencies
*CL : Cas Latency
- B3(DDR333)
133MHz
166MHz
- A2(DDR266A)
133MHz
133MHz
- B0(DDR266B)
100MHz
133MHz
Speed @CL2
Speed @CL2.5
Part No.
Org.
Max Freq.
Interface
Package
K4H560438D-GC(L)B3
64M x 4
B3(DDR333@CL=2.5)
SSTL2
60 ball FBGA
K4H560438D-GC(L)A2
A2(DDR266@CL=2)
K4H560438D-GC(L)B0
B0(DDR266@CL=2.5)
K4H560838D-GC(L)B3
32M x 8
B3(DDR333@CL=2.5)
SSTL2
60 ball FBGA
K4H560838D-GC(L)A2
A2(DDR266@CL=2)
K4H560838D-GC(L)B0
B0(DDR266@CL=2.5)
K4H561638D-GC(L)B3
16M x 16
B3(DDR333@CL=2.5)
SSTL2
60 ball FBGA
K4H561638D-GC(L)A2
A2(DDR266@CL=2)
K4H561638D-GC(L)B0
B0(DDR266@CL=2.5)
ORDERING INFORMATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4H560438D-TCB0 | Quad Wide Bandwidth High Output Drive Single Supply Op Amp 16-SOIC 0 to 70 |
| K4H560438D-TLA0 | Quad Wide Bandwidth High Output Drive Single Supply Op Amp 16-SOIC 0 to 70 |
| K4H560438D-TLA2 | Quad Wide Bandwidth High Output Drive Single Supply Op Amp 16-PDIP 0 to 70 |
| K4H560438D-TLB0 | Quad Wide Bandwidth High Output Drive Single Supply Op Amp 16-PDIP 0 to 70 |
| K4H560438E-NLA2 | Quad Wide Bandwidth High Output Drive Single Supply Op Amp 20-HTSSOP 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4H560438D-TCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H560438D-TCB3 | 制造商:Samsung Semiconductor 功能描述:DRAM Chip DDR SDRAM 256M-Bit 64Mx4 2.5V 60-Pin FBGA Tray |
| K4H560438D-TLA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H560438D-TLA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H560438D-TLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
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