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參數資料
| 型號： | K4H560438E-GCCC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DIODE ZENER SINGLE 300mW 29.8Vz 5mA-Izt 0.02503 0.05uA-Ir 23 SOT-23 3K/REEL |
| 中文描述： | 256Mb的電子芯片的DDR 400內存規格60Ball FBGA封裝（x4/x8） |
| 文件頁數： | 1/26頁 |
| 文件大小： | 291K |
| 代理商： | K4H560438E-GCCC |
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256Mb
DDR SDRAM
Rev. 2.2 Mar. ’03
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Four banks operation
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
Data I/O transactions on both edges of data strobe
Edge aligned data output, center aligned data input
LDM,UDM/DM for write masking only
Auto & Self refresh
7.8us refresh interval(8K/64ms refresh)
Maximum burst refresh cycle : 8
60 Ball FBGA package
Key Features
Operating Frequencies
*CL : Cas Latency
- B3(DDR333)
133MHz
166MHz
- A2(DDR266A)
133MHz
133MHz
- B0(DDR266B)
100MHz
133MHz
Speed @CL2
Speed @CL2.5
Part No.
Org.
Max Freq.
Interface
Package
K4H560438D-GC(L)B3
64M x 4
B3(DDR333@CL=2.5)
SSTL2
60 ball FBGA
K4H560438D-GC(L)A2
A2(DDR266@CL=2)
K4H560438D-GC(L)B0
B0(DDR266@CL=2.5)
K4H560838D-GC(L)B3
32M x 8
B3(DDR333@CL=2.5)
SSTL2
60 ball FBGA
K4H560838D-GC(L)A2
A2(DDR266@CL=2)
K4H560838D-GC(L)B0
B0(DDR266@CL=2.5)
K4H561638D-GC(L)B3
16M x 16
B3(DDR333@CL=2.5)
SSTL2
60 ball FBGA
K4H561638D-GC(L)A2
A2(DDR266@CL=2)
K4H561638D-GC(L)B0
B0(DDR266@CL=2.5)
ORDERING INFORMATION
相關PDF資料 |
PDF描述 |
|---|---|
| K4H560438E-GLA2 | DIODE ZENER SINGLE 300mW 33Vz 5mA-Izt 0.02503 0.05uA-Ir 27 SOT-23 3K/REEL |
| K4H560438E-NCA2 | 256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) |
| K4H560838E | 10-Bit, 32 kSPS ADC Serial Out, uProcessor Periph./Standalone, 11 Ch. 20-PDIP |
| K4H560838E-TCAA | 256Mb E-die DDR SDRAM Specification 66 TSOP-II |
| K4H560838E-TCB3 | 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, 11 Ch. 20-PDIP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| K4H560438E-GLA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 60Ball FBGA (x4/x8) |
| K4H560438E-GLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 60Ball FBGA (x4/x8) |
| K4H560438E-GLB3 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 60Ball FBGA (x4/x8) |
| K4H560438E-NC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) |
| K4H560438E-NC/LA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) |
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