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參數(shù)資料
| 型號： | K7D801871B-HC25 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 & 512Kx18 SRAM |
| 中文描述： | 256Kx36 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 270K |
| 代理商： | K7D801871B-HC25 |
Rev 4.0
256Kx36 & 512Kx18 SRAM
- 1 -
January. 2002
K7D801871B
K7D803671B
Document Title
8M DDR SYNCHRONOUS SRAM
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
Rev No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 0.3
Rev. 0.5
Rev. 0.6
Rev. 0.7
Rev. 1.0
Rev. 2.0
Rev. 3.0
Rev. 4.0
Remark
Advance
Advance
Advance
Advance
Prelimary
Prelimary
Prelimary
Final
Final
Final
Final
History
-Initial document.
-ZQ tolerance changed from 10% to 15%
-Stop Clock Standby Current condition changed from
V
IN
=V
DD
-0.2V or 0.2V fixed to V
IN
=V
IH
or V
IH
-V
DDQ
Max. changed to 2.0V
SA0, SA1 defined for Boundary Scan Order
-Deleted -HC16 part(Part Number, Idd, AC Characterisctics)
- Absolute Maximum ratings V
DDQ
changed from 3.13V to 2.825V
- LBO input level changed from High/Low to V
DDQ
/V
SS
- Stop Clock Standby Current condition changed
from K=Low, K=High to K=Low, K=Low
- t
CHQV/
t
CLQV
changed from 0.1ns to 0.2ns for -33 part
from 0.1ns to 0.2ns for -30 part
from 0.1ns to 0.25ns for -25part
- t
CHQX/
t
CLQX
changed from -0.3ns to -0.2ns for -33 part
from -0.3ns to -0.2ns for -30 part
from -0.4ns to -0.25ns for -25part
-
t
CHQZ/
t
CLQZ
changed from 0.1ns to 0.2ns for -33 part
from 0.1ns to 0.2ns for -30 part
from 0.1ns to 0.25ns for -25part
-
t
KXCH
changed from 1.8ns to 1.7ns for -33 part
-
t
KXCL
changed from 1.8ns to 1.7ns for -33 part
- Clarification on the features and the timing waveforms regarding the
burst controllability.
- Recommended DC operating conditions for Clock added.
- AC test conditions for V
DDQ
=1.8V and Single ended clock added.
(AC Test Conditions 2)
- Package thermal characteristics added.
- Add-HC35 part(Part Number, Idd, AC Characteristics)
- Absolute Maximum Rating VDDQ changed from 2.825V to 2.4V
- V
CM-CLK
Min changed from 0.6V to 0.68V
- Add-HC37 part(Part Number, Idd, AC Characteristics)
Draft Data
July. 2000
Aug. 2000
Oct. 2000
Nov. 2000
Jan. 2001
Feb. 2001
Mar. 2001
May. 2001
Sep. 2001
Jan. 2002
Jan. 2002
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7D801871B-HC30 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC33 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC35 | 256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC37 | 256Kx36 & 512Kx18 SRAM |
| K7D803671B | 256Kx36 & 512Kx18 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7D801871B-HC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC35 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D801871B-HC37 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
| K7D803671B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 SRAM |
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