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參數資料
| 型號： | K7R161884B-FC20 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36 & 1Mx18 QDR II b4 SRAM |
| 中文描述： | 512Kx36 |
| 文件頁數： | 1/18頁 |
| 文件大小： | 418K |
| 代理商： | K7R161884B-FC20 |
- 1 -
Rev 3.1
July. 2004
512Kx36 & 1Mx18 QDRTM II b4 SRAM
K7R163684B
K7R161884B
Document Title
512Kx36-bit,1Mx18-bit QDRTM II b4 SRAM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.0
2.0
3.0
3.1
Remark
Advance
Preliminary
Final
History
1. Initial document.
1. Change the Boundary scan exit order.
2. Correct the Overshoot and Undershoot timing diagram.
1. Change JTAG Block diagram
1. Add the speed bin (-25)
1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
1. Add the power up/down sequencing comment.
2. Update the DC current parameter (Icc and Isb).
3. Change the Max. speed bin from -33 to -30.
1. Change the ISB1.
1. Final spec release
1. Delete the x8 Org.
2. Delete the 300MHz speed bin
1. Add the 300MHz speed bin
1. Change the stand-by current(ISB1)
before
after
Isb1
-30 :
230
260
-25 :
210
240
-20 :
190
220
-16 :
170
200
Speed Bin
From
To
-30
200
230
-25
180
210
-20
160
190
-16
140
170
Draft Date
Oct. 17. 2002
Dec. 16, 2002
Dec. 26, 2002
Jan. 27, 2003
Mar. 20, 2003
April. 4, 2003
June. 20, 2003
Oct. 20. 2003
Oct. 31, 2003
Nov. 28, 2003
June. 18, 2004
July. 28, 2004
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| K7R161884B-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 QDR II b4 SRAM |
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