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參數(shù)資料
| 型號(hào)： | KAB02D100M-TLGP |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Tantalum Conformal-Coated Capacitor; Capacitance: 22uF; Voltage: 10V; Packaging: Tape & Reel |
| 中文描述： | 多芯片封裝存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 1/72頁(yè) |
| 文件大小： | 1378K |
| 代理商： | KAB02D100M-TLGP |
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KAB0xD100M - TxGP
Revision 1.11
August 2003
- 1 -
MCP MEMORY
SEC Only
Document Title
Multi-Chip Package MEMORY
64M Bit (8Mx8/4Mx16) Dual Bank NOR Flash / 128M Bit (8Mx16) NAND Flash / 32M Bit
(2Mx16) UtRAM
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision No.
0.0
0.1
0.2
0.3
1.0
1.1
1.11
Remark
Preliminary
Preliminary
Preliminary
Final
Final
Final
Final
History
Initial Draft
Inserted No ECC condition in NAND Flash
Endurance (1page)
: 1,000 Program/Erase Cycles Maximum without ECC
Program Flow (39page)
: Excluded "Read Verify" step after programming in this condition
<Common>
Revised T
BIAS
(43page)
from "-25 to 85" to "-40 to 125"
Revised V
IL
(43page)
from max. 0.6V to max. 0.5V
Revised V
OH
(43page)
from min. 2.4V to min. 2.3V
Revised IOL(43page)
from 0.1mA to max. 2.1mA
Revised IOH(43page)
from -0.1mA to max. -1.0mA
<NAND>
Revised the internal voltage that disables all functions(37page)
from 2V to 1.3V
Revised power-up and power-down recovery time(37page)
from min. 1
μ
s to min. 10
μ
s
Revised write cycle time(tWC)(59page)
from 50ns to min. 45ns
Combined ALE to RE Delay in ID read and in Read cycle(59page)
from min. 20ns and 50ns to min. 10ns
Revised RE Access Time(t
REA
)(59page)
from max. 35ns to max. 30ns
Excluded min. value of RE High to Output Hi-Z(t
REH
)(59page)
Inserted RE or CE
F
High to Output Hold(t
OH
) with min. 15ns(59page)
Revised timing diagram
Finalize
Revised <NOR>
- Release the stand-by current from typ. 5uA(max. 18uA) to typ.
10uA(max. 30uA).
Revised <NAND>
- Corrected Some typos in the timing diagram
Draft Date
March 20, 2002
March 28, 2002
March 28, 2002
June 17, 2002
October 15, 2002
June 18, 2003
August 14, 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.
http://samsungelectronics.com/semiconductors/products/products_index.html
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KAB02D100M-TNGP | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY |
| KAB03D100M-TLGP | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY |
| KAB03D100M-TNGP | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY |
| KAB04D100M-TLGP | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY |
| KAB04D100M-TNGP | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY |
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