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參數(shù)資料
| 型號： | KK82C55 |
| 廠商： | KODENSHI CORP. |
| 英文描述： | CHMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| 中文描述： | CHMOS可編程外圍接口 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大小： | 416K |
| 代理商： | KK82C55 |
TECHNICAL DATA
K K
82C55
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
The Integral
KK
82C55AN is a high-performance, CHMOS version of the industry standard
KK8
2C55AN general purpose programmable I/O device which is designed for use with all Intel and
most other microprocessors. It provides 24 I/O pins which may be individually programmed in 2
groups of 12 and used in 3 major modes of operation.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or
outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the
remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bi-
directional bus configuration.
FEATURES
Compatible with all Intel and Most Other Microprocessors
High Speed, Zero Wait State Operation with 8MHz 8086/88 and 80186/188
24 Programmable I/O Pins
Low Power CHMOS
Completely TTL Compatible
Control Word Read-Back Capability
Direct Bit Set/Reset Capability
2.5mA DC Drive Capability on all I/O Port Outputs
Available in 40-Pin DIP
Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
GROUP
A
CONTROL
DATA
BUS
BUFFER
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
GROUP
B
PORT
B
(8)
GROUP
B
PORT C
LOWER
(4)
GROUP
A
PORT C
UPPER
(4)
GROUP
A
PORT
A
(8)
PA
7
-PA
0
PC
7
-PC
4
PC
3
-PC
0
PB
7
-PB
0
D
7
-D
0
RD
WR
A
1
A
0
CS
Reset
8 BIT
INTERNAL
DATA BUS
Figure 1
1.
2.
3.
4.
5.
6.
7.
8.
9.
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PA
4
PA
5
PA
6
PA
7
WR
Reset
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
V
CC
PB
7
PB
6
PB
5
PB
4
PB
3
PA
3
PA
2
PA
1
PA
0
RD
CS
V
SS
A
1
A
0
PC
7
PC
6
PC
5
PC
4
PC
0
PC
1
PC
2
PC
3
PB
0
PB
1
PB
2
Figure 2
1
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