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參數資料
| 型號： | KM4216C258 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256K x 16 Bit CMOS Video RAM(256K x 16 位 CMOS視頻RAM) |
| 中文描述： | 256K × 16位的CMOS視頻RAM（256K × 16位的CMOS視頻內存） |
| 文件頁數： | 1/41頁 |
| 文件大小： | 772K |
| 代理商： | KM4216C258 |
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KM4216C258
CMOS VIDEO RAM
Rev. 0.1 (Mar. 1998)
The RAM array consists of 512 bit rows of 8192 bits.
It operates like a conventional 256K x 16 CMOS DRAM.
The RAM port has a write per bit mask capability.
Data may be written with New and Old Mask. The RAM port has
a Fast Page mode access with Extended Data out, Byte/Word
write operation and Block Write capabilities.
The SAM port consists of sixteen 512 bit high speed shift regis-
ters that are connected to the RAM array through a 8192 bit data
transfer gate. The SAM port has serial read capability.
Data may be internally transferred from the RAM to SAM port
using read, and programmable (Stop Register) Split Transfers.
Refresh is accomplished by familiar DRAM refresh modes.
The KM4216C258 supports RAS-only, Hidden, and CAS-
before-RAS refresh for the RAM port. The SAM port does not
require refresh.
All inputs and I/O
′
s are
TTL
level compatible. All address lines
and data inputs are latched on chip to simplify system design.
The outputs are unlatched to allow greater system flexibility.
Dual port Architecture
256K x 16 bits RAM port
512 x 16 bits SAM port
Performance range :
Fast Page Mode with Extended Data Out
RAM Read, Write, Read-Modify-Write
Serial Read (SR)
Read / Real time read transfer (RT, RRT)
Split Read Transfer with Stop Operation (SRT)
2 CAS Byte / Word Read / Write Operation
8 Column Block Write (BW) and Write-per-Bit
with Masking Operation (New and Old Mask)
CAS-before-RAS, RAS-only and Hidden Refresh
Common Data I/O Using three state RAM Output Control
All Inputs and Outputs TTL Compatible
Refresh : 512 Cycle/8ms
Single +5V
±
10% Supply Voltage
Plastic 64-Pin 525mil SSOP (0.8mm pin pitch)
GENERAL DESCRIPTION
The Samsung KM4216C258 is a CMOS 256K x 16 bit Dual Port
DRAM. It consists of a 256K x 16 dynamic random access mem-
ory (RAM) port and 512 x 16 static serial access memory (SAM)
port. The RAM and SRAM port operate asynchronously except
during data transfer between the ports.
Speed
Parameter
-5
-6
-7
RAM access time (
t
RAC
)
50ns
60ns
70ns
RAM access time (
t
CAC
)
15ns
15ns
20ns
RAM cycle time (
t
RC
)
85ns
104ns
130ns
RAM page cycle (
t
HPC
)
20ns
24ns
28ns
SAM access time (
t
SCA
)
15ns
15ns
17ns
SAM cycle time (
t
SCC
)
18ns
18ns
20ns
RAM active corrent
KM4216C258
130m
120m
110m
SAM active current
KM4216C258
40mA
50mA
45mA
FEATURES
256K x 16 Bit CMOS Video RAM
PIN CONFIGURATION
(TOP VIEWS)
1
2
3
4
5
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7
8
9
10
11
12
13
14
15
16
17
18
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23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
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58
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56
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53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
CC
DT/OE
V
SS
SQ
0
W
0
/DQ
0
SQ
1
W
1
/DQ
1
SQ
2
SQ
3
SQ
4
SQ
5
SQ
6
SQ
7
W
2
/DQ
2
W
3
/DQ
3
W
4
/DQ
4
W
5
/DQ
5
W
6
/DQ
6
W
7
/DQ
7
V
CC
V
SS
V
CC
V
SS
CASL
WB/WE
RAS
A
8
A
7
A
6
A
5
A
4
V
CC
SC
SE
V
SS
SQ
15
W
15
/DQ
15
SQ
14
W
14
/DQ
14
V
CC
SQ
13
W
13
/DQ
13
SQ
12
W
12
/DQ
12
V
SS
SQ
11
W
11
/DQ
11
SQ
10
W
10
/DQ
10
V
CC
SQ
9
W
9
/DQ
9
SQ
8
W
8
/DQ
8
V
SS
DSF
N.C
CASU
QSF
A
0
A
1
A
2
A
3
V
SS
64-Pin 525 mil
SSOP
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