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參數資料
| 型號： | KM718V890 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx18 Synchronous SRAM(256Kx18位同步靜態 RAM) |
| 中文描述： | 256Kx18同步SRAM（256Kx18位同步靜態內存） |
| 文件頁數： | 1/15頁 |
| 文件大小： | 315K |
| 代理商： | KM718V890 |
KM718V890
256Kx18 Synchronous SRAM
- 1 -
Rev 1.0
May. 1998
Document Title
256Kx18-Bit Synchronous Pipelined Burst SRAM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
1.0
History
Initial draft
Change speed symbol 6.0/6.7/7.5/8.5 to 60/67/75/85,
Change 7.5 bin to 7.2
Change speed bin from 60/67/75/85 to 72/85/10.
Change DC characteristics V
DD
condition from 3.3V
±
5% to 3.3V+10%/-5%
Change Input/output leackage currant for
±1μ
A to
±
2
μ
A,
Insert Note 4 at AC timing characteristics.
Modify Read timing & Power down cycle timing.
Change I
SB2
value from 10mA to 20mA.
Remove Low power version.
Change Undershoot spec
from -3.0V(pulse width
≤
20ns) to -2.0V(pulse width
≤
t
CYC
/2)
Add Overshoot spec 4.6V((pulse width
≤
t
CYC
/2)
Change Vih max from 5.5V to Vdd+0.5V
Change I
SB2
value from 20mA to 30mA.
Change V
DD
condition from V
DD
=3.3V+10%/-5% to V
DD
=3.3V+0.3V/-0.165V.
Modify DC characteristics( Input Leakage Current test Conditions)
form V
DD
=V
SS to
V
DD
to Max.
Final spec Release
Draft Date
Decmber. 15. 1997
February. 02. 1998
February. 06. 1998
February. 12. 1998
April. 14. 1998
May. 13. 1998
May. 14. 1998
May. 15. 1998
REMARK
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Final
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