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參數資料
| 型號： | L5510 |
| 廠商： | 意法半導體 |
| 英文描述： | HIGHLY INTEGRATED, AUTOMATED SINGLE-CHIP DRIVE MANAGER AND DISK DRIVE CONTROLLER |
| 中文描述： | 高度集成的，自動化的單芯片驅動管理器和磁盤驅動器控制器 |
| 文件頁數： | 1/3頁 |
| 文件大小： | 53K |
| 代理商： | L5510 |
1/3
L5510
December 2004
This is preliminary information on a new product now in development. Details are subject to change without notice.
1
■
Synchronous DMA (modes 0-4)
■
Fast IDE PIO modes 0-4
■
ATA Multiword DMA modes 0-2; supports 60 ns
cycle time
■
Basic level of ATAPI support
■
IORDY for PIO flow control
■
Automatic ATA R/W command execution
■
Automatic ATA task file updates
■
128-byte host FIFO to/from buffer
■
LBA or CHS TASK File Modes
■
Read/write cache support with interrupt
suppression
■
Programmable IRQ automation for different
BIOS implementations
■
Provides logic for daisy chaining two embedded
disk drive controllers
■
Full BIOS compatibility
■
On-chip selectable 4/8/12 mA host drivers
ATA Host Interface Block
2
■
60 MIPS operation
■
16-bit, fixed-point DSP
■
16x16-bit, 2’s complement parallel multiplier
with 32-bit product
■
Single-cycle multiply and accumulate
■
36-bit ALU with two 36-bit accumulators
■
Bit manipulation unit with 2 additional
accumulators
■
6 K words on-chip RAM
DSP Core
3
■
16-bit wide buffer data bus
■
16 Mbit x 16 SDRAM support; up to 150 Mbyte/
s buffer bandwidth
■
Automated Data Flow Management (ADFM)
automates disk/host transfers
■
Dynamic segment size switching
■
Auto-Write cache support
■
Automatic servo split address adjustment
■
Disk LBA counter
Buffer Controller Block
4
■
Optimized ECC with up to six burst on-the-fly
(OTF) correction
■
Programmable 480-bit Reed-Solomon code
EDAC Block
■
Programmable 3-, 4-, or 5-way interleaving with
6 to 12 8-bit symbols per interleave
■
Optional 3 or 5 byte CRC support
■
Guarantee up to 233-bit single burst or six 33-bit
bursts OTF correction in <3 sector time
■
ECC seeding validating servo and head track
position
■
AIC-8381 polynomial support for backward
compatibility
5
■
Enhanced Headerless Architecture (EDSA)
■
Up to 450 Mbits/s data rate, byte-wide NRZ
■
31 x 3 byte flexible high-speed RAM- based
sequencer
■
Defect skipping and/or embedded servo
capabilities with Constant Density Recording
(CDR)
■
128-byte disk FIFO to/from buffer
■
Disk error condition summary bit added to
reduce error detection time
■
Three-index timer
■
MR and PRML channel support
Disk Controller Block
6
■
Automatic internal sector mark generation
■
Programmable servo burst sequencer
■
Programmable servo timing mark sequencer
■
Flexible gating and control generation
■
User programmable control output pins
■
Allows servo format flexibility
■
Synchronous servo support
Servo Block
DATA BRIEF
HIGHLY INTEGRATED, AUTOMATED SINGLE-CHIP
DRIVE MANAGER AND DISK DRIVE CONTROLLER
REV. 1
Figure 1. Package
Table 1. Order Codes
Part Number
L5510
AIC-5465-DIE
Package
TFBGA240
DIE
TFBGA240
DIE
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