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| 型號(hào)： | L8575 |
| 英文描述： | Dual-Resistive,Low-Cost Subscriber Line Interface Circuit(SLIC) |
| 中文描述： | 雙電阻，低成本用戶線接口電路（SLIC） |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 633K |
| 代理商： | L8575 |
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L8575
Dual-Resistive, Low-Cost SLIC
Advance Data Sheet
March 1997
22
Lucent Technologies Inc.
Applications
(continued)
Serial Data Interface
(continued)
Figure 7 shows the timing characteristics and requirement definitions.
12-3305(F).ar2
Figure 7. Timing Requirements for CLK, EN, DI, and DO
Table 12. Truth Table for EN and CLK
Table 13. Output DATA Bit Definition
EN
1
0
↓
CLK
↓
↓
X
Function
Shift register clocked, QN = QN – 1; latches unaffected.
Channel data latched into shift register; latches unaffected.
Contents of shift register transferred to output latches.
DATA Bit
D0A
D1A
D2A
D3A
D0B
D1B
D2B
D3B
Output
D0A
D1A
RDRA
RDTA
D0B
D1B
RDRB
RDTB
Output Bit Definition
Latch output state D0A (refer to Operating States section).
Latch output state D1A (refer to Operating States section).
Ringing relay driver A is on (RDRA low = relay energized) when D2A = 1.
Test relay driver A is on (RDTA low = relay energized) when D3A = 1.
Latch output state D0B (refer to Operating States section).
Latch output state D1B (refer to Operating States section).
Ringing relay driver B is on (RDRB low = relay energized) when D2B = 1.
Test relay driver B is on (RDTB low = relay energized) when D3B = 1.
DI
EN
CLK
DO
t
SDE
t
WEN
t
HDC
t
SDC
t
HEC
t
SEC
t
WCK
t
WCK
t
PCO
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