- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367494 > L9313 Line Interface and Line Access Circuit Full-Feature SLIC and Ringing for TR-57 Applications PDF資料下載
參數(shù)資料
| 型號(hào)： | L9313 |
| 英文描述： | Line Interface and Line Access Circuit Full-Feature SLIC and Ringing for TR-57 Applications |
| 中文描述： | 線路接口和線路接入電路全功能SLIC和敲響訓(xùn)練班- 57應(yīng)用 |
| 文件頁(yè)數(shù)： | 19/40頁(yè) |
| 文件大小： | 746K |
| 代理商： | L9313 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)當(dāng)前第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)
Data Sheet
September 2001
Full-Feature SLIC and Ringing Relay for TR-57 Applications
L9313 Line Interface and Line Access Circuit
Agere Systems Inc.
19
Electrical Characteristics
(continued)
Logic Inputs and Outputs, V
DD
= 5.0 V
Table 9. Logic Inputs and Outputs
Timing Requirements
Table 10. Timing Requirements
Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in
when the LATCH control input goes low. Data must be set up t
SU
ns before LATCH goes low and held t
HL
ns after
LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, and B2. The
data control inputs at B0, B1, and B2 may only be changed when LATCH is high. NSTAT supervision output is not
controlled by the LATCH control input.
12-3526(F)
Figure 3. Timing Requirements
Parameter
Symbol
Min
Typ
Max
Unit
Input Voltages:
Low Level
High Level
Input Current:
Low Level (V
DD
= 5.25 V, V
I
= 0.4 V)
High Level (V
DD
= 5.25 V, V
I
= 2.4 V)
Output Voltages (CMOS):
Low Level (V
DD
= 4.75 V, I
OL
= 180
μ
A)
High Level (V
DD
= 4.75 V, I
OH
=
–
20
μ
A)
V
IL
V
IH
–
0.5
2.0
0.4
2.4
0.7
V
DD
V
V
I
IL
I
IH
—
—
—
—
±
50
±
50
μ
A
μ
A
V
OL
V
OH
0
2.4
0.2
—
0.4
V
CC
V
V
Parameter
Symbol
t
SU
t
HL
Min
200
50
Typ
—
—
Max
—
—
Unit
ns
ns
Minimum Setup Time from B0, B1, B2 to LATCH
Minimum Hold Time from LATCH to B0, B1, B2
t
SU
t
HL
LATCH
B0, B1,
B2, B3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L9350 | Single Peripheral Driver |
| L9355 | Dual Peripheral Driver |
| L9500A | High-Voltage Ringing SLIC for VolP Applications |
| L9653M | Analog IC |
| L9654M | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L9324 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Peripheral Driver |
| L9326 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| L-932P3C | 制造商:Kingbright Corporation 功能描述: |
| L-9331 | 制造商:Ideal Industries Inc 功能描述:L-9331 |
| L9332 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Quad intelligent power low side switch |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。