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參數(shù)資料
型號: L9953XPTR
廠商: STMICROELECTRONICS
元件分類: 運(yùn)動(dòng)控制電子
英文描述: BRUSH DC MOTOR CONTROLLER, 10 A, PDSO36
封裝: ROHS COMPLIANT, SSOP-36
文件頁數(shù): 20/38頁
文件大小: 535K
代理商: L9953XPTR
L9953 / L9953XP
Functional description of the SPI
Doc ID 14278 Rev 3
17
OUT8 – HS
on/off
If a bit is set the selected
output driver is switched
on. If the corresponding
PWM enable bit is set
(Input Register 1) the
driver is only activated if
PWM1 (PWM2) input
signal is high. The outputs
of OUT1-OUT5 are half
bridges. If the bits of HS-
and LS-driver of the same
half bridge are set, the
internal logic prevents that
both drivers of this output
stage can be switched on
simultaneously in order to
avoid a high internal
current from VS to GND.
In test mode (CSN>9.5V)
this bit combinations are
used to multiplex internal
signals to the DO-output.
LS3 HS3 LS4 HS4 LS5 HS5 CM/PWM2
00
5A Iref
11
00
Tsens1
00
11
00
Tsens2
11
00
Tsens3
00
11
Tsens4
11
11Vbgp
OUT8 – HS
over-current
In case of an over-current
event the corresponding status
bit is set and the output driver
is disabled. If the over-current
Recovery Enable bit is set
(Input Register 1) the output
will be automatically
reactivated after a delay time
resulting in a PWM modulated
current with a programmable
duty cycle (Bit 21).
If the over-current recovery bit
is not set the microcontroller
has to clear the over-current
bit (Reset Bit) to reactivate the
output driver.
16
x (don’t care)
0
15
OUT7 – HS
on/off
OUT7 – HS
over-current
14
OUT6 – HS
on/off
OUT6 – HS
over-current
13
x (don’t care)
0
12
x (don’t care)
0
11
x (don’t care)
10
OUT5 – HS
on/off
OUT5 – HS
over-current
9
OUT5 – LS
on/off
OUT5 – LS
over-current
8
OUT4 – HS
on/off
OUT4 – HS
over-current
7
OUT4 – LS
on/off
OUT4 – LS
over-current
6
OUT3 – HS
on/off
OUT3 – HS
over-current
5
OUT3 – LS
on/off
OUT3 – LS
over-current
4
OUT2 – HS
on/off
OUT2 – HS
over-current
3
OUT2 – LS
on/off
OUT2 – LS
over-current
2
OUT1 – HS
on/off
OUT1 – HS
over-current
1
OUT1 – LS
on/off
OUT1 – LS
over-current
0
No error bit
A logical NOR-combination of
all bits 1 to 22 in both status
registers.
Table 19.
SPI - input data and Status registers 0 (continued)
Bit
Input register 0 (write)
Status register 0 (read)
Name
Comment
Name
Comment
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