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參數資料
| 型號： | LA17000M |
| 元件分類： | 接收器 |
| 英文描述： | AM/FM, AUDIO SINGLE CHIP RECEIVER, PQFP80 |
| 封裝： | 14 X 14 MM, QFP-80 |
| 文件頁數： | 11/54頁 |
| 文件大小： | 830K |
| 代理商： | LA17000M |
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LA17000M
No. 6522-19/54
Description of DI Control Data
No.
Control block/Data
Description
Related data
Programmable divider data
This data sets divisor for the programmable divider. P15 is a binary value that is
designated as the MSB. The LSB changes depending on DVS and SNS.
P0 to P15
* DVS = 1 (DVS = 0: Prohibited)
These values select the signal input pin (PLL IN) for the programmable divider,
and switch the input frequency range.
DVS, SNS
* For details, refer to “Programmable Divider Configuration.”
Sub-charge pump
This data controls the sub-charge pump.
control data
PDC, PDC1
* The sub-charge pump can be used to form a high-speed lockup circuit in
combination with PD0 and PD1 (main charge pump).
For details, refer to the page on charge pump.
Reference divider data
This is the reference frequency (fref) selection data.
R0 to R3
*1: Prohibited when X’tal OSC = 10.25 MHz.
*2: PLL INHIBIT (backup mode)
The programmable divider block stops, the PLL IN pin is pulled down to
GND, and the charge pump output goes to the floating state.
Continued on next page.
DVS
SNS
ISB
Divisor setting (N)
1
P0
272 to 65535
DVS
SNS
Input pin
Input pin frequency range
1
PLLIN
10 to 160 MHz
PDC1
PDC0
Subcharge pump status
0
*
High impedance
1
0
Charge pump on (when unlocked)
1
Charge pump on (normal operation)
R3
R2
R1
R0
Reference frequency
0
Prohibited
00
01
50
00
10
25
00
11
25
0
1
0
12.5
0
1
0
1
6.25
0
1
0
3.125
0
1
3.125
10
00
10
1
0
1
9
*1
10
5
10
11
1
0
9
*1
1
0
1
30
*1
1
0
*2 PLL INHIBIT + X’tal OSC STOP
1
*2 PLL INHIBIT
UL0, UL1,
DLC
(2)
(1)
(3)
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