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參數(shù)資料
| 型號(hào)： | LA5695M |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大?。?/td> | 64K |
| 代理商： | LA5695M |
Equivalent Circuit Block Diagram
[Trigger signal generation circuit]
When the input pulse (50% duty) is held low or high, OUT1 is set high. At other times, this circuit generates the trigger
signal.
[Output delay circuit and output latch circuit]
The OUT pin is set low when the delay time set by the external capacitor (connected to the output delay time setting pin)
elapses after the input goes high. Furthermore, once the output goes low, it is held in that state until the power supply is
turned off.
[V
CC
voltage abnormality detection circuit]
These circuits monitor the V
CC
voltage and set OUT low if the voltage exceeds the set range.
No. 6519-6/8
LA5695M
ILA00202
13
14
8
11
TEST
4
IN2
2
IN1
6
IN3
3
IN5
1
IN4
12
IN8
7
IN7
5
IN6
IN
OUT1
10
C2
9
VCC
Output delay
circuit and
output latch
circuit
V
CC
voltage
abnormality
detection circuit
V
CC
voltage
abnormality
detection circuit
Trigger signal
generation
circuit
*
Sets OUT low when V
CC
> 6.5 V (typ)
*
Sets OUT low when
V
CC
< 3.0 V (typ)
C1
OUT
GND
Output delay
time setting
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