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參數資料
| 型號： | LA9240M |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數： | 2/20頁 |
| 文件大小： | 320K |
| 代理商： | LA9240M |
11. DEFECT
The mirrored surface level is maintained by the capacitor for LF2 (pin 59); when a drop in the EFM signal (RFSM output)
reaches 0.35 V or more, a high signal is output to DEF (pin 49). If DEF (pin 49) goes high, the tracking servo enters THLD
mode. In order to prevent the tracking servo from entering THLD mode when a defect is detected, prevent DEFECT from
being output by either shorting DEF (pin 49) to GND, or shorting LF2 (pin 59) to GND. The DEFECT output is driven by
constant current (approximately 100 A).
12. Microprocessor interface
Because the Reset (Nothing) command initializes the LA9240M, it must be used carefully.
The LA9240M command acceptance (mode switching) timing is defined by the internal clock (4.23 MHz divided to 130 kHz)
after the falling edge of CE (RWC); therefore, when commands are sent consecutively, CE must go low for at least 10 sec.
The 4.23 MHz clock is required for that reason. 2BYTE-COMMAND DETECT and 2BYTE-COMMAND RESET are used
only for the purpose of masking two-byte data.
All instructions can be input by setting CE high and sending commands synchronized with the CL clock from the
microprocessor to DAT (pin 52) in LSB first format. Note that the command is executed at the falling edge of CE.
13. Reset circuit
The power-on reset is released when VCC exceeds approximately 2.8 V.
14. Pattern design notes
To prevent signal jump-in from CV
+ (pin 40) to RFSM (pin 41), a shielding line is necessary in between.
15. VCC /REF/GND/NC
VCC1 (pin 64)
: RF system
VCC2 (pin 56)
: SERVO system, DIGITAL system
AGND (pin 22)
: RF system, SERVO system
DGND (pin 45)
: DIGITAL system
NC (pin 48)
: No connection
VR (Pin 58)
: Reference voltage
EFM signal
(RFSM output)
LF2 (pin 59)
DEF (pin 49)
Timing
* The DSP pin names are shown in parentheses.
LA9240M
No.5482 - 10/20
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