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參數資料
| 型號： | LC171W03-A4 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | SPECIFICATION FOR APPROVAL |
| 中文描述： | 規范批準 |
| 文件頁數： | 13/28頁 |
| 文件大小： | 732K |
| 代理商： | LC171W03-A4 |
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Product Specification
13 / 28
LC171W03
Liquid Crystal Display
Ver. 0.0
Jan.10, 2002
3-3. Signal Timing Specifications
This is the signal timing required at the input of the User connector. All of the interface signal timing should be
satisfied with the following specifications for it’s proper operation.
Table 7. Timing Table
Note
:
Hsync period and Hsync width-active should be even number times of t
CLK
. If the value is odd number times
of t
CLK
, display control signal can be asynchronous. In order to operate this LCM a Hsync, Vsync and DE
(Data Enable) signals should be used.
1. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rates.
2. Vsync, Hsync should be keep the above specification.
3. Hsync Period, Hsync Width and Horizontal Back Porch should be any times of a character number (8).
tCLK
-
32
16
tWH
Width
Note 1)
PAL : 47~53Hz
NTSC : 57~63Hz
tHP
-
22
5
-
Vertical Blank
-
160
32
-
Horizontal Blank
tHP
-
13
2
tVBP
Vertical Back Porch
tCLK
-
80
8
tHBP
Horizontal Back Porch
-
48
8
tHFP
Horizontal Front Porch
768
768
768
tVV
Vertical Valid
-
2
1
tVFP
Vertical Front Porch
Hz
63
60
47
fV
Frequency
-
7
2
tWV
Width
tCLK
-
1440
1312
tHP
Period
Hsync
tHP
-
790
773
tVP
Period
Vsync
1280
1280
1280
tHV
Horizontal Valid
DE
(Data
Enable)
MHz
82.00
68.25
54.00
Frequency
ns
18.52
14.65
12.20
tCLK
Period
DCLK
Note
Unit
Max
Typ
Min
Symbol
ITEM
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