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| 型號： | LC4512V-10F256I |
| 文件頁數： | 10/57頁 |
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Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
10
ORP Bypass and Fast Output Multiplexers
The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the
ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also
allows the register output to bypass the ORP to achieve faster t
CO
.
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus
maintenance circuitry. Figure 8 details the I/O cell.
Figure 8. I/O Cell
Each output supports a variety of output standards dependent on the V
also be con
fi
gured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the V
CCO
supplied to its I/O bank. The I/O standards supported are:
LVTTL
LVCMOS 1.8
LVCMOS 3.3
3.3V PCI Compatible
LVCMOS 2.5
CCO
supplied to its I/O bank. Outputs can
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
con
fi
gured to be a Pull-up Resistor.
Each ispMACH 4000 device I/O has an individually programmable output slew rate control bit. Each output can be
individually con
fi
gured for the higher speed transition (~3V/ns) or for the lower noise transition (~1V/ns). For high-
speed designs with long, unterminated traces, the slow-slew rate will introduce fewer re
fl
ections, less noise and
keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be
used to achieve the highest speed. The slew rate is adjusted independent of power.
Global OE Generation
Most ispMACH 4000 family devices have a 4-bit wide Global OE Bus, except the ispMACH 4032 device that has a
2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or
GOE pins. Each signal that drives the bus can optionally be inverted.
GOE 0
GOE 1
GOE 2
GOE 3
From ORP
*Global fuses
From ORP
To Macrocell
To GRP
VCC
V
CCO
V
CCO
*
*
*
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相關代理商/技術參數 |
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| LC4512V-10F256I1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4512V-10FN256I | 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC4512V-10FN256I1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4512V-10FT256I | 功能描述:CPLD - 復雜可編程邏輯器件 ispJTAG 3.3V 10nsIND 512MC 208 I/O RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC4512V-10FTN256I | 功能描述:CPLD - 復雜可編程邏輯器件 ispJTAG 3.3V 10nsIND 512MC 208 I/O RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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