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參數資料
型號: LC72131KM
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
封裝: 0.300 INCH, MFP-20
文件頁數: 3/22頁
文件大?。?/td> 200K
代理商: LC72131KM
LC72131K, 72131KM
No.A0788-11/22
Continued from preceding page.
No.
Control block/data
Functions
Related data
(8)
Phase comparator
control data
DZ0, DZ1
Controls the phase comparator dead zone.
Dead zone width: DZA<DZB<DZC<DZD
(9)
Clock time base
TBC
Setting TBC to one causes an 8Hz, 40% duty clock time base signal to be output from the BO1
pin. (BO1 data is invalid in this mode.)
BO1
(10)
Charge pump control
data
DLC
Forcibly controls the charge pump output.
Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO
oscillator stopping, deadlock can be cleared by forcing the charge pump output to low and
setting Vtune to VCC. (This is the deadlock clearing circuit.)
(11)
IF counter control
data
IFS
This data must be set 1 in normal mode.
IFS Though if this value is set to zero, the system enters input sensitivity degradation mode,
and the sensitivity is reduced to 10 to 30mVrms.
* See the “IF Counter Operation” item for details.
(12)
LSI test data
TEST0 to 2
LSI test data
TEST0
TEST1
These values must all be set to 0.
TEST2
These test data are set to 0 automatically after the power-on reset.
(13)
DNC
Don’t care. This data must be set to 0.
DO Control Data (Serial Data Output) Structure
[3] OUT Mode
DZA
DZB
DZC
DZD
Dead zone mode
0
1
0
1
0
1
DZ0
DZ1
Normal operation
Forced low
0
1
Charge pump output
DLC
C1
C2
C3
(2)
U
N
LO
CK
(1)
IN
-PO
R
T
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
(3)
IF
-C
TR
C14
C15
C16
C17
C18
C19
UL
I1
I2
C0
address
Fist Data OUT
0
1
0
1
0
1
DO
: Must be 0.
DI
0
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參數描述
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