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參數資料
| 型號： | LC72133M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | MFP20 |
| 文件頁數： | 7/23頁 |
| 文件大小： | 147K |
| 代理商： | LC72133M |
Programmable Divider Structure
Note: * Don’t care.
1. Programmable Divider Calculation Examples
FM, 50 kHz steps (DVS = 1, SNS = *, FMIN selected)
FM RF = 80.0 MHz (IF = –10.7 MHz)
FM VCO = 69.3 MHz
PLL fref = 25 kHz (R0 to R1 = 1, R2 to R3 = 0)
69.3 MHz (FM VCO)
÷ 25 kHz (fref) ÷ 2 (FMIN: divide-by-two prescaler) = 1386 → 056A (HEX)
SW, 5 kHz steps (DVS = 0, SNS = 1, AMIN high speed side selected)
SW RF = 21.75 MHz (IF = +450 kHz)
SW VCO = 22.20 MHz
PLL fref = 5 kHz (R0 = R2 = 0, R1 = R3 = 1)
22.2 MHz (SW VCO)
÷ 5 kHz (fref) = 4440 → 1158 (HEX)
MW, 10 kHz steps (DVS = 0, SNS = 0, AMIN low-speed side selected)
MW RF = 1000 kHz (IF = +450 kHz)
MW VCO = 1450 kHz
PLL fref = 10 kHz (R0 to R2 = 0, R3 = 1)
1450 kHz (MW VCO)
÷ 10 kHz (fref) = 145 → 091 (HEX)
No. 5427-15/23
LC72133M, 72133V
DVS
SNS
Input pin
Set divisor
Actual divisor: N
Input frequency range (MHz)
A1
*
FMIN
272 to 65535
Twice the set value
10 to 130
B
0
1
AMIN
272 to 65535
The set value
2 to 40
C
0
AMIN
4 to 4095
The set value
0.5 to 10
fvco/N
fref
PD
E
fvco = fref
× N
Programmable
Divider
(C)
(B)
(A)
Swallow
Counter
4bits
12bits
1/2
DVS
SNS
AMIN
FMIN
A11928
A11929
A
650
0101011010100000
*
1
1100
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
SNS
DVS
CTE
XS
R0
R1
R2
R3
A11930
8511
000110101000100010
0101
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
SNS
DVS
CTE
XS
R0
R1
R2
R3
A11931
190
****
10001001000000
0001
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
SNS
DVS
CTE
XS
R0
R1
R2
R3
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