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參數資料
| 型號： | LC72710LW |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數： | 4/7頁 |
| 文件大小： | 168K |
| 代理商： | LC72710LW |
LC72710W, 72710LW
No.6166-4/30
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
DMA cycle wait
tCYDM
RD, DREQ
420
nS
RD low-level width (DMA)
tWRDM
RD
300
nS
Notes: Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 280ns (minimum).
[LC72710W]
Electrical Characteristics at VDD=+4.5 to +5.5V, within the allowable operating ranges
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
VOH1
IO=2mA, BCK, FCK, BLOCK, FLOCK,
VDD-0.4
V
High-level output voltage
CRC4, CLK16, DATA
VOH2IO=4mA, INT, RDY, DREQ, D0 to D15
VDD-0.4
V
VOL1IO=2mA, Pins for which VOH1 applies
0.4
V
Low-level output voltage
VOL2IO=4mA, Pins for which VOH2 applies
0.4
V
VOL3IO=2mA, DO, INT
0.4
V
IIH1
VIN=5.5V, A0/CL, A1/CE, A2/DI, RST,
1.0
A
High-level input current
STNBY
IIH2VIN=VDDD, All input pins other than IIH1
1.0
A
Low-level input current
IIL
VIN=VSSD, All input pins
-1.0
A
Input resistance
RMPX
MPXIN -Vssa f=100kHz
50
k
Reference supply voltage output
Vref
Vref, Vdda=5V
2.5
V
Bandpass filter center frequency
Fc
FLOUT
76.0
kHz
-3 dB bandwidth
Fbw
FLOUT
19.0
kHz
Group delay
Dgd
FLOUT
-7.5
+7.5
s
Gain
FLOUT-MPXIN, f=76kHz
20
dB
ATT1
FLOUT, f=50kHz
25
dB
Stop band attenuation
ATT2
FLOUT, f=100kHz
15
dB
ATT3
FLOUT, f=30kHz
50
dB
ATT4
FLOUT, f=150kHz
50
dB
Output off leakage current
IOFF
VO=VDDD, DO
5.0
A
Hysteresis voltage
VHYS
A0/CL, A1/CE, A2/DI, A3, CS, RD, WR,
0.1VDDDV
DACK, IOCNT1, IOCNT2, RST, STNBY
Internal feedback resistor
Rf
XIN, XOUT
1.0
M
Current drain
IDD
18
25
mA
[LC72710LW]
Electrical Characteristics at VDD=+2.7 to +3.6V, within the allowable operating ranges
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
VOH1
IO=1mA, BCK, FCK, BLOCK, FLOCK,
VDD-0.4
V
High-level output voltage
CRC4, CLK16, DATA
VOH2IO=2mA, INT, RDY, DREQ, D0 to D15
VDD-0.4
V
VOL1IO=1mA, Pins for which VOH1 applies
0.4
V
Low-level output voltage
VOL2IO=2mA, Pins for which VOH2 applies
0.4
V
VOL3IO=1mA, DO, INT
0.4
V
IIH1
VIN=5.5V, A0/CL, A1/CE, A2/DI, RST,
1.0
A
High-level input current
STNBY
IIH2VIN=VDDD, All input pins other than IIH1
1.0
A
Low-level input current
IIL
VIN=VSSD, All input pins
-1.0
A
Input resistance
RMPX
MPXIN -Vssa f=100kHz
50
k
Reference supply voltage output
Vref
Vref, Vdda=3V
1.5
V
Bandpass filter center frequency
Fc
FLOUT
76.0
kHz
-3 dB bandwidth
Fbw
FLOUT
19.0
kHz
Group delay
Dgd
FLOUT
-7.5
+7.5
s
Gain
FLOUT-MPXIN, f=76kHz
20
dB
ATT1
FLOUT, f=50kHz
25
dB
Stop band attenuation
ATT2
FLOUT, f=100kHz
15
dB
ATT3
FLOUT, f=30kHz
50
dB
ATT4
FLOUT, f=150kHz
50
dB
Output off leakage current
IOFF
VO=VDDD, DO
1.0
A
Continued on next page.
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