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參數資料
| 型號： | LC72710W |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數： | 2/7頁 |
| 文件大小： | 168K |
| 代理商： | LC72710W |
LC72710W, 72710LW
No.6166-2/30
Specifications
Absolute Maximum Ratings at Ta=25°C, VSS=0V. Items in parentheses refer to the LC72710LW.
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VDD
(-0.3 to +5.5) -0.3 to +7.0
V
Input voltage
VIN1
A0/CL, A1/CE, A2/DI, RST, STNBY
-0.3 to +7.0
V
VIN2
Pins other than VIN1
-0.3 to VDD +0.3
V
Output voltage
VOUT1
DO
-0.3 to +7.0
V
VOUT2
Pins other than VOUT1
-0.3 to VDD +0.3
V
Output current
IOUT1
INT, RDY, DREQ, and D0 to D15
0 to 4.0
mA
IOUT2
Pins other than IOUT1
0 to 2.0
mA
Allowable output current (total)
ITTL
Total for all the output pins
20
mA
Allowable power dissipation
Pd max
Ta ≤ 85°C
200
mW
Operating temperature
Topr
--40 to +85
°C
Storage temperature
Tstg
--55 to +125
°C
[LC72710W]
Allowable Operating Ranges at Ta=-40 to +85°C, VSS=0V
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
VDD
4.5
5.5
V
High-level input voltage
VIH1
A0/CL, A1/CE, A2/DI, RST, STNBY
0.7VDD
5.5
V
VIH2
DACK, WR, RD, CS, SP, BUSWD, A3, IOCNT1, IOCNT2
0.7VDD
VDD
V
Low-level input voltage
VIL1
Pins for which VIH1 applies
VSS
0.3VDD
V
VIL2
Pins for which VIH2 applies
VSS
0.3VDD
V
Oscillator frequency
FOSC
This IC operates with a frequency precision of ±250 ppm
7.2
MHz
XIN input sensitivity
VXI
With a sine wave input to XIN, capacitor coupling,
400
1500
mVrms
VDD=+4.5 to +5.5V
Input amplitude
VMPX
With a 100% modulated composite signal input to
150
400
mVrms
MPXIN, VDD=+4.5 to +5.5V
[Serial I/O]
Clock low-level period
tCL
A0/CL
0.7
S
Clock high-level period
tCH
A0/CL
0.7
S
Data setup time
tSU
A0/CL, A2/DI
0.7
S
Data hold time
tHD
A0/CL, A2/DI
0.7
S
CE wait time
tEL
A0/CL, A1/CE
0.7
S
CE setup time
tES
A0/CL, A1/CE
0.7
S
CE hold time
tEH
A0/CL, A1/CE
0.7
S
Data latch change time
tLC
A1/CE
0.7
S
Data output time
tDDO
DO, A0/CL
277
555
nS
CRC4 change time
tCRC
CRC4, A0/CL
0.7
S
[LC72710W]
Allowable Operating Ranges: Parallel Interface at Ta=-40 to +85°C, VSS=0V
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
[Parallel I/O]
Address to RD setup
tSARD
A0/CL, A1/CE, A2/DI, A3, RD
20
nS
RD to address hold
tHARD
A0/CL, A1/CE, A2/DI, A3, RD, tWRDL=>250ns
-20
nS
RD low-level width
tWRDL1
RD
250
nS
RD low-level width (when RDY is used)
tWRDL2
RD
100
nS
RD cycle wait
tCYRD
A0/CL, A1/CE, A2/DI, A3, RD
150
nS
RDY width (Register read)
tWRDY
RDY
60
210
nS
RD data hold
tRDH
RD, DATn
0
nS
Address to WR setup
tSAWR
A0/CL, A1/CE, A2/DI, A3, WR
20
nS
WR to address hold
tHAWR
A0/CL, A1/CE, A2/DI, A3, WR
20
nS
WR cycle wait
tCYWR
A0/CL, A1/CE, A2/DI, A3, WR
150
nS
WR low-level width
tWWRL
WR
200
nS
WR data hold
tWDH
WR, DATn
0
nS
RDY output delay
tDRDY
RD, RDY
0
30
nS
Corrected output RD width
tWDRD1
RD (BUSWD=L 8bits)
300
nS
RD (BUSWD=H 16bits)
540
nS
Corrected output RD width
tWDRD2
RD (BUSWD=L 8bits)
100
nS
(when RDY is used)
RD (BUSWD=H 16bits)
300
nS
Continued on next page.
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