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參數(shù)資料
型號(hào)： LC72711LW
廠商： SANYO SEMICONDUCTOR CO LTD
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, SQFP-64
文件頁(yè)數(shù)： 23/26頁(yè)
文件大小： 157K
代理商： LC72711LW
LC72711W, 72711LW
No.6167-6/26
Block Diagram
Pin Functions
Pin No.
Pin
Function
I/O
Pin circuit
3
IOCNT1
Data bus I/O control 1 (SP=low)*1
4
IOCNT2
Data bus I/O control 2 (SP=low)*1
13
DACK
DMA acknowledge (SP=low)*1
38
WR
Write control signal (SP=low)*1
39
RD
Read control signal (SP=low)*1
40
A0/CL
Address input
0 (SP=low) CCB CL input (SP=High)
Input
41
A1/CE
1 (SP=low) CCB CE input (SP=High)
42
A2/DI
2 (SP=low) CCB DI input (SP=High)
43
A3
3 (SP=low)*1
44
CS
Chip select input (SP=L)*1
46
RST
System reset input (negative logic)
45
STNBY
Standby mode (positive logic)
47
SP
SP=low: parallel, SP=high: serial
48
BUSWD
BUSWD=low: 8 bits, BUSWD=high: 16bits
60
TEST
The test pin must be connected to the digital system ground (VSS).
58
TPC1
Must be connected to the digital system power supply (VDD) or ground
Input
(VSS) in normal operation.
59
TPC2
As above
61
TOSEL1
As above
62
TOSEL2
As above
49
TIN
As above
5
CLK16
Clock regeneration monitor
6
DATA
Demodulated data monitor
9
FCK
Frame start signal output
10
BCK
Block start signal output
7
FLOCK
Outputs a high level during frame synchronization
Output
8
BLOCK
Outputs a high level during block synchronization
11
CRC4
Level 4 CRC detection result output
33
INT
External CPU interrupt request output
12
DREQ
DMA request signal
16
RDY
Read ready signal
Continued on next page.
LPF
MPXIN
7.2MHz
Vref
XIN
Vssa
Vdda
XOUT
RST
CLK16
DATA
BCK
FCK
FLOCK
BLOCK
STNBY
Vssd
Vddd
LPF
76kHz
BPF
(SCF)
Vref
IOCNT1
DACK
DREQ
IOCNT2
CRC4
FLOUT
CIN
VREF
CS
RD
WR
RDY
INT
BUSWD
TIN
SP
A3
DO
A2/DI
A1/CE
A0/CL
D0
to
D15
PN decoding
Memory array
Data
Address
Error correction:
layer 2 CRC
Anti-aliasing
filter
Timing
control
Synchronization
regeneration
MSK correction
circuit
Clock
regeneration
2T delay
1T delay
Output control (CPU interface) and
layer 4 CRC detection circuit
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