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參數資料
| 型號： | LC72722 |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP24 |
| 封裝： | SDIP-24 |
| 文件頁數： | 14/15頁 |
| 文件大小： | 114K |
| 代理商： | LC72722 |
No. 5602-8/15
LC72722, 72722M, 72722PM
3. Synchronization and RAM address reset (1 bit): SYR
Initial value: SYR =0
Caution: 1. To apply a synchronization reset, set SYR to 1 temporarily using the CCB, and then set it back to 0 again using the CCB.
The circuit will start synchronization capture operation at the point SYR is set to 0.
2. The SYR pin (pin 24) also provides an identical reset control operation. Applications can use either method. However, the control method
that is not used must be set to 0 at all times. Any pulse with a width of over 250 ns will suffice.
3. A reset must be applied immediately after the reception channel is changed. If a reset is not applied, reception data from the previous
channel may remain in memory.
4. Data read out after a synchronization reset is read out starting with the backward protection block data preceding the establishment of
synchronization.
SYR
Synchronization detection circuit
RAM
0
Normal operation (reset cleared)
Normal write (See the description of the OWE bit.)
1
Forced to the unsynchronized state (synchronization reset)
After the reset is cleared, start writing from the data prior to the
establishment of synchronization, i.e. the data in backward protection.
Initial value: OWE = 0
Initial values: EC0 = 0, EC1 = 1, EC2 = 0, EC3 = 0, EC4 = 1
Caution: 1. If soft-decision A or soft-decision B is specified, soft-decision control will be performed even if the number of bits corrected is set to 0 (error
detection only). With these settings, data will be output for blocks with no errors.
2. As opposed to soft-decision B, the soft-decision A setting suppresses soft decision error correction.
4. RAM write control (1 bit): OWE
5. Error correction method setting (5 bits): EC0 to EC4
OWE
RAM write conditions
0
Only data for which synchronization had been established is written.
1
Data for which synchronization not has been established (unsynchronized data) is also written. (However, this applies when SYR = 0.)
E
Number of
C C C
bits corrected
0
1
2
0
0 0 (error detection only)
1
0
1 or fewer bits
0
1
0
2 or fewer bits
1
0
3 or fewer bits
0
1
4 or fewer bits
1
0
1
5 or fewer bits
0
1
Illegal value
1
Illegal value
E
C C
Soft-decision setting
3
4
0
Mode 0: Hard decision
1
0
Mode 1: Soft decision A
0
1
Mode 2: Soft decision B
1
Illegal value
6. Intermittent DO output setting
SP0
SP1
DO output state
0
DO goes low when one or more blocks of data are written to memory.
1
0
DO goes low when 4 or more blocks of data are written to memory.
0
1
DO goes low when 8 or more blocks of data are written to memory.
1
DO goes low when 12 or more blocks of data are written to memory.
7. Crystal oscillator frequency selection (1 bit): XS
XS = 0: 4.332 MHz
XS = 1: 8.664 MHz
Initial value: XS = 0
Initial values: SP0 = 0, SP1 = 0
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相關代理商/技術參數 |
參數描述 |
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| LC72722M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Single-Chip RDS Signal-Processing System LSI |
| LC72722PM | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Single-Chip RDS Signal-Processing System LSI |
| LC72722PM_12 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Single-Chip RDS Signal-Processing System IC |
| LC72722PM-MPB-E | 功能描述:音頻 DSP RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| LC72722PMS | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Single-Chip RDS Signal-Processing System IC |
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