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參數資料
| 型號： | LC72722M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數： | 15/15頁 |
| 文件大小： | 114K |
| 代理商： | LC72722M |
No. 5602-9/15
LC72722, 72722M, 72722PM
8. Demodulation circuit phase control (2 bits): PL0, PL1
Initial values: PL0 = 0, PL1 = 1
Caution: 1. When PL0 is 0 (normal operation), the IC detects the presence or absence of the ARI signal and reproduces the RDS data by automatically
controlling the demodulation phase with respect to the reproduced carrier. However, the initial phase following a synchronization reset is set
by PL1.
2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90° (PL1 = 0) or 0° (PL1 = 1), allowing RDS
data to be reproduced. When ARI is not present, PL1 should be set to 0, since the RDS data is reproduced by detecting at a phase of 90°
with respect to the reproduced carrier. When ARI is present, PL1 should be set to 1, since detection is at 0°. In cases where the ARI
presence is known in advance, more stable reproduction can be achieved by fixing the demodulation phase in this manner.
PL0
PL1
Demodulation circuit phase control
0
0/1
<Normal operation> when ARI presence or absence is unclear.
1
0
If the circuit determines that the ARI signal is absent: 90° phase
1
If the circuit determines that the ARI signal is present: 0° phase
9. RDS/RBDS (MMBS) selection (1 bit): RM
Initial value: RM = 0
—: Open, q
q, q: Output enabled (q = reverse polarity)
Initial values: PT0 = 1, PT1 = 1, PT2 = 0 (mode 3)
Caution: 1. When PT2 is set to 1, T6 (ERROR/57K/TP), T7 (CORREC/ARI-ID/TA) SYNC, and RDS-ID pins change to active high.
2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors to output data.
TP = Traffic program code
RM
RBDS support
Decoding method
0
None
Only RDS data is decoded correctly (Offset word E is not detected.)
1
Provided
RDS and MMBS data is decoded correctly (Offset word E is also detected.)
10. Output pin settings (3 bits): PT0 to PT2
These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins.
P
T3
T4
T5
T6
T7
Mode
T
0
1
2
RDCL
RDDA
RSFT
ERROR
57K
TP
BE1
CORREC
ARI-ID
TA
BE0
0
—
1
0
—
q
—
q
—
2
0
1
0
q
—
q
—
q
—
3
1
0
q
—
q
—
4
0
1
—
q
—
q
5
1
0
1
—
q
—
q
—
6
0
1
q
—
q
—
q
—
7
1
q
—
q
—
Mode 1 (PT2 = 0)
Pin T6 (TP)
TP = 0 detected
High (1)
TP = 1 detected
Low (0)
TA = Traffic announcement code
Mode 1 (PT2 = 0)
Pin T7 (TA)
TA = 0 detected
High (1)
TA = 1 detected
Low (0)
Mode 2 (PT2 = 0)
Pin T7 (ARI-ID)
No SK
High (1)
SK present
Low (0)
Mode 3 (PT2 = 0)
Pin T6 (ERROR)
Pin T7 (CORREC)
Correction not possible
Low (0)
Errors corrected
High (1)
Low (0)
No errors
High (1)
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| LC72722PM | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Single-Chip RDS Signal-Processing System LSI |
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