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參數資料

2. Field determination circuit

Since the field is determined by the phase difference between the falling edges of the V and H signals, these signals

must be input with the timing shown in the figure.

Here, a and b must be: a = 0.02 to 0.40 H, b = 0.60 to 0.98 H.

The synchronization signal pulse widths are: tWV > 1 s, tWH > 1 s.

Clamping Pulses

1. A/D converter clamping

Since clamping pulses are output with the timing shown in the figure, they must set to fall in the pedestal range. On a

reset or during standby mode, the H-S input signal becomes a positive polarity signal, and is output as such.

Note: Here, t3 and t4 must be: t3 > 0 s, t4 > 0.5 s.

2. D/A converter clamping

The digital data for the regions A is as follows:

Y D/A converter input:

000000

R-Y D/A converter input: 100000

B-Y D/A converter input: 100000

Clamping is applied on the main screen horizontal synchronization signal.

No. 4872-17/19

LC74401E, 74402, 74402E

相關代理商/技術參數	參數描述
LC74403E	制造商:未知廠家制造商全稱:未知廠家功能描述:Peripheral IC
LC7441	制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Picture-in-picture Controller for TVs and VCRs
LC74411	制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PIP Controller
LC74411N	制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PIP Controller
LC74411NE	制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PIP Controller

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