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參數資料
| 型號： | LC7441NE |
| 元件分類： | 畫面疊加 |
| 英文描述： | PICTURE-IN-PICTURE IC, PQFP64 |
| 封裝： | QIP-64 |
| 文件頁數： | 4/20頁 |
| 文件大小： | 410K |
| 代理商： | LC7441NE |
LC7441N, 7441NE
No.3941–12/20
Serial Data Interface
When SER/PIN is HIGH, SD/FHP, SCK/FVP and SDE/
STL function as the serial-interface data, clock and data-
enable inputs, respectively, as shown in the following
figure. After SDE/STL goes LOW, data bits D00 to D07
are the internal register address, and D10 to D17, the
Internal Registers
The internal control registers are shown in the following
table. Note that the lower four bits of the address byte
register data. After the data has been received, the
address is automatically incremented, and D20 to D27
are the data for the next register. After SDE/STL goes
from LOW to HIGH to LOW, address selection re-
occurs.
determine the register address, and the upper four bits are
ignored.
s
e
r
d
A
n
o
i
t
i
s
o
p
t
i
B
76543210
H
0Y
B
SR
A
V
K
WD
L
I
FT
U
O
KR
A
V
S
O
PL
T
SR
P
V
FR
P
H
F
H
1Y
B
SI
R
P2
T
U
O
K1
T
U
O
K2
L
T
S1
L
T
SR
P
V
FR
P
H
F
H
8E
P
I
W
VE
P
I
W
H5
P
V4
P
V3
P
V2
P
V1
P
V0
P
V
H
9R
A
RL
U
M5
P
H4
P
H3
P
H2
P
H1
P
H0
P
H
A2
K
W1
K
W5
K
W
Y4
K
W
Y3
K
W
Y2
K
W
Y1
K
W
Y0
K
W
Y
H
B2
R
A
V
K
W1
R
A
V
K
W5
K
W
R4
K
W
R3
K
W
R2
K
W
R1
K
W
R0
K
W
R
H
C1
S
F
D
V0
S
F
D
V5
K
W
B4
K
W
B3
K
W
B2
K
W
B1
K
W
B0
K
W
B
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