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參數資料
| 型號： | LC7442 |
| 元件分類： | 畫面疊加 |
| 英文描述： | PICTURE-IN-PICTURE IC, PDIP64 |
| 封裝： | SDIP-64 |
| 文件頁數： | 6/23頁 |
| 文件大小： | 317K |
| 代理商： | LC7442 |
LC7442, 7442E
Specifications
Absolute Maximum Ratings at Ta = 25 ±2°C, VSS = 0 V
Paramater
Symbol
Ratings
Unit
Maximum supply voltage
VDD max
–0.3 to +7.0
V
Maximum input voltage
VIN max
–0.3 to VDD + 0.3
V
Maximum output voltage
VOUT max
–0.3 to VDD + 0.3
V
Allowable power dissipation
Pd1 max (DIP version)
500
mW
Pd2 max (QFP version)
350
mW
Operating temperature
Topr
–10 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Allowable Operating Ranges at Ta = –10 to +70°C, VSS = 0 V
Ratings
Paramater
Symbol
Conditions
min
typ
max
Unit
Power supply voltage
VDD
4.5
5.0
5.5
V
Input high level voltage
VIH1
CMOS levels
0.7 VDD
V
VIH2
TTL levels
2.2
V
Input low level voltage
VIL1
CMOS levels
0.3 VDD
V
VIL2
TTL levels
0.8
V
Reference voltage
VREF
VREF pin
3.4
0.8 VDD
VDD
V
Electrical Characteristics at Ta = 25 ±2°C, VDD = 5 V ±10%, VSS = 0 V
Ratings
Paramater
Symbol
Conditions
min
typ
max
Unit
Output high level voltage
VOH1
IOH = –1 mA; Pins KCP and OCP
VDD – 1
V
VOH2
IOH = –1 mA; Pins other than KCP and OCP
VDD – 1
V
Output low level voltage
VOL1
IOL = 1 mA; Pins KCP and OCP
1.0
V
VOL2
IOL = 2 mA; Pins other than KCP and OCP
0.4
V
Operating current dissipation
IDDD
RES: H
The DVSS pin
20
mA
IDDA
OV, KV: 60 Hz
The AVSS pin
21
mA
IDDO
OH, KH: 15 kHz
The OVSS pin
2
mA
IDDK
A/D data: 1010
The KVSS pin
2
mA
Output unloaded
Static current dissipation
IDDS
RES: L,
10
A
Input pin DC, output unloaded
Input leakage current
ILK
VI = VDD, VSS
–1
1
A
Output leakage current
IOZ
VI = VDD, VSS; Pins KCP and OCP
–1
1
A
D/A output resistance
RDA
150
Note: There are 4 power supply pin systems.
The power supplies are DVDD, AVDD, OVDD, and KVDD, and they must be identical. Descriptions are for VDD.
The grounds are DVSS, AVSS, OVSS and KVSS, and they must be identical. Descriptions are for VSS.
Switching Characteristics at Ta = 25 ±2°C, VDD = 5 V ±10%, VSS = 0 V
Ratings
Paramater
Symbol
min
typ
max
Unit
Vertical sync signals
Pulse width
tVW
1
s
Rise time
tVR
50
ns
Fall time
tVF
50
ns
Horizontal sync signals
Pulse width
tHW
1
s
Rise time
tHR
50
ns
Fall time
tHF
50
ns
Serial data interface
Serial clock
Pulse width
tSCW
200
ns
Rise time
tSCR
50
ns
Fall time
tSCF
50
ns
Data setup
tDSU
100
ns
Data hold
tDH
30
ns
Interval
tSCI
2
s
Control
Pulse width
tCW
200
ns
Rise time
tCR
50
ns
Fall time
tCF
50
ns
Setup
tCSU
200
ns
Hold
tCH
200
ns
No. 4412-14/22
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