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參數(shù)資料
| 型號： | LC74751 |
| 元件分類： | 畫面疊加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDIP22 |
| 封裝： | SDIP-22 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大小： | 540K |
| 代理商： | LC74751 |
No. 5396-9/15
LC74751
Address 190 (0BE hexadecimal)
DA
Register
Contents
Notes
0 to C
State
Function
0
PHASE0
0
1
PHASE1
0
1
2
PHASE2
0
1
3
SIGMD0
0
1
4
SIGMD1
0
1
5
SYSRST
0
The IC is reset by a low level on the CS pin, and the
1
Resets all registers and turns display off.
reset state is cleared by a high level on that pin.
6
MUTE
0
Normal output
1CVIN is cut and CVOUT is fixed at the pedestal level.
7
DSPON
0
Character display off
1
Character display on
8
OSCSTP
0
Crystal oscillator and LC oscillator circuits are not stopped.
Only valid in external synchronization mode
1
Stops the crystal oscillator and LC oscillator circuits.
when character display is off.
9
2fsc/
0
Clock frequency: 2fsc
Crystal oscillator circuit frequency
4fsc/
1
Clock frequency: 4fsc
A
LC/
0
The LC oscillator is used for the dot clock.
The OSCIN pin must be tied to VDD if the LC
XTAL
1
The crystal oscillator is used for the dot clock.
oscillator circuit is not used.
B
INT/
0
Interlaced (262.5 H per field: NTSC, 312.5 H per field: PAL)
Switches interlaced and noninterlaced display.
NON
1
Noninterlaced (263 H per field: NTSC, 313 H per field: PAL)
SIGMD1
SIGMD0
Signal format
00
NTSC
01
PAL
10
PAL-M
11
PAL-N
PHASE2 PHASE1 PHASE0
Background color (phase)
NTSC
PAL (PAL-M, N)
000
π/2
± π/2
001
π
In phase
010
3π/2
π/2
01
1
In phase
±π
100
π/4
±3π/4
101
3π/4
±π/4
110
5π/4
π/4
111
7π/4
±3π/4
Note: The states of all registers are set to zero when the IC is reset by the RST pin.
Background color
The phase of the background color with
respect to the color burst signal.
-+
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相關(guān)代理商/技術(shù)參數(shù) |
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| LC74761_11 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:On-Screen Display LSI |
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